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Admitting and ejecting flits in wormhole-switched networks on chip

IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第5期1卷 546-556页

作者： Lu, Z. Jantsch, A. Royal Inst Technol Dept Elect Comp & Software Syst S-16440 Kista Sweden

Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirectly, techniques for admitting and ejecting flits exert a significant impact on network performance and switch cost. Different flit-admission and flit-ejection micro-architectures are investigated. In particular, for flit admission, a novel coupling scheme which binds a flit-admission queue with a physical channel (PC) is presented. This scheme simplifies the switch crossbar from 2p x p to (p + 1) x p, where p is the number of PCs per switch. For flit ejection, a p-sink model that uses only p flit sinks to eject flits is proposed. In contrast to an ideal ejection model which requires p . v flit sinks (v is the number of virtual channels per PC), the buffering cost of flit sinks becomes independent of v. The proposed flit-admission and flit-ejection schemes are evaluated with both uniform and locality traffic in a 2D 4 x 4 mesh network. The results show that both schemes do not degrade network performance in terms of average packet latency and throughput if the flit injection rate is slower than 0.57 flit/cycle/node.

关键词： multiprocessor interconnection networks flits ejection physical channel wormhole-switched networks average packet latency networks on chip flits admission network-on-chip

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Reliability and latency Analysis of Sliding Network Coding With Re-Transmission

Reliability and Latency Analysis of Sliding Network Coding W...

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IEEE Wireless Communications and Networking Conference (WCNC)

作者： Wu, Fangzhou Tan, Zhiyuan Zhu, Huiying Dong, Pengpeng Huawei Technol Co Ltd Wireless Network RAN Res Dept Shanghai Peoples R China

ISBN: (纸本)9781665491228

Future networks are expected to support various ultra-reliable low-latency communications via wireless links. To avoid the loss of packets and keep the low latency, sliding network coding (SNC) is an emerging technology by generating redundant packets that are the linear combination of the original data packets from the current block and some previous blocks. However, how to take the advantage of re-transmission for SNC is still an open problem since higher reliability could be achieved at the expense of large latency caused by round-trip time (RTT). To deal with this issue, in this paper, we consider the idea of adjusting the transmission phase and the number of the redundant packets for SNC with re-transmission. Specifically, If RTT is large, most of the redundant packets are sent at the first transmission, otherwise, re-transmission will be used. We first derive a concise and tight lower bound of the block error probability of SNC without re-transmission. Then, based on the bound, the theoretical expressions of the proposed retransmission schemes are derived regarding the block error probability, the average code length, and the average packet latency. Results show that the proposed SNC with re-transmission improves block error probability and keeps the low latency.

关键词： average packet latency convolutional network coding first-block error probability re-transmission sliding network coding

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Bandwidth Optimization in Asynchronous NoCs by Customizing Link Wire Length

Bandwidth Optimization in Asynchronous NoCs by Customizing L...

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IEEE International Conference on Computer Design

作者： You, Junbok Gebhardt, Daniel Stevens, Kenneth S. Univ Utah Elect & Comp Engn Salt Lake City UT 84112 USA Univ Utah Sch Comp Salt Lake City UT 84112 USA

ISBN: (纸本)9781424489350

The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver. We explore the benefit to NoC performance when this property is used to increase bandwidth on specific links that carry the most traffic of an SoC design. Two methods are used to accomplish this: specifying router locations on the floorplan, and adding pipeline latches on long links. Energy and latency characteristics of an asynchronous NoC are compared to a similarly-designed synchronous NoC. The results indicate that the asynchronous network has lower energy, and link-specific bandwidth optimization has improved the average packet latency. Adding pipeline latches to congested links yields the most improvement. This link-specific optimization is applicable not only to the router and network we present here, but any asynchronous NoC used in a heterogeneous SoC.

关键词： IP cores NoC performance SoC design asynchronous NoC link asynchronous NoCs average packet latency bandwidth optimization bandwidth requirement integrated circuit design latency characteristics link wire length network-on-chip network-on-chip pipeline latches router locations traffic properties

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Design of Efficient Router with Low Power and Low latency for Network on Chip

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Circuits and Systems 2016年第4期7卷 339-349页

作者： M. Deivakani D. Shanthi Department of Electronics and Communication Engineering PSNA College of Engineering and Technology Dindigul India Department of Computer Science Engineering PSNA College of Engineering and Technology Dindigul India

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

关键词： Network on Chip Router Processing Element Wireless Link Power Consumption average packet latency

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Hybrid interconnection networks for reducing hardware cost and improving path diversity based on fat-trees and hypercubes

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2023年第19期35卷

作者： Wang, Yaodong Li, Yamin Hosei Univ Grad Sch CIS Tokyo Japan Hosei Univ Dept Comp Sci Tokyo Japan

Fat-tree topologies are widely used in interconnect network designs for parallel supercomputers. In the classic fat-tree, compute nodes are connected to leaf stage switches by links. Given a large number of compute nodes, many switches and links are required, resulting in high hardware costs. To solve this problem, this paper proposes two hybrid topologies, k-Cube k-Ary n-Tree (CAT) and Mirrored k-Cube k-Ary n-Tree (MiCAT), based on fat-tree and hypercube. Instead of connecting k compute nodes directly to a leaf switch, we connect a k-cube to the switch, and each switch in the k-cube part connects k compute nodes. That is, this k-cube consists of 2(k) - 1 switches and k(2(k)-1) compute nodes. We give the shortest path routing algorithms and evaluate the path diversity, cost, performance, and average packet latency of CAT and MiCAT. The results show that CAT and MiCAT can save up to 87% switches and 80% links in a large-scale parallel system, k=n=8 for example, compared to fat-trees, and meanwhile, both CAT and MiCAT have higher path diversities than fat-trees.

关键词： average packet latency fat-tree hardware cost hypercube interconnection network path diversity routing algorithm

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