Civil infrastructures are constantly exposed to external hazards, such as earthquakes, flooding, and storm surges. These hazards underscore the need to estimate the risk of critical facilities due to catastrophic even...
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Civil infrastructures are constantly exposed to external hazards, such as earthquakes, flooding, and storm surges. These hazards underscore the need to estimate the risk of critical facilities due to catastrophic events. Given uncertainties associated with hazards, their propagation, and the complex interdependent nature of civil infrastructures, probabilistic risk assessment (PRA) has been gaining popularity for risk-informed decision-making, both under normal and extreme scenarios. One of the key steps of PRA is systems analysis, where fault and event trees are used to propagate the fragilities of structures, systems, and components (SSCs) to estimate the system-level risk. This paper presents the development of selective scenarios with increasing complexity from small to large realistic networks to conduct a comparative analysis among different fault tree analysis (FTA) algorithms. Some of these application scenarios can serve as benchmarks for future studies. Computational efficiency and accuracy are quantified and compared for a suite of selected algorithms. The results show that the performance of these algorithms is affected by the structure of the fault tree under consideration. In a fewcases, the key sources of complexity in algorithms that influence the speed and memory/storage requirements are also identified.
Product code has been proven as an efficient choice for achieving high net coding gain (NCG) at extremely low bit error rates (BER) in fiber communication systems. Compared to the hard-decision product decoders, it ha...
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ISBN:
(纸本)9798350373530;9798350373523
Product code has been proven as an efficient choice for achieving high net coding gain (NCG) at extremely low bit error rates (BER) in fiber communication systems. Compared to the hard-decision product decoders, it has been demonstrated that decoders based on soft-assisted decoding algorithms can achieve excellent decoding performance with only a slight increase in area. However, existing decoders tend to have high power dissipation and large component decoder area due to the fully-parallel architecture. Therefore, further efforts are needed to achieve efficient hardware implementation. In this paper, a low-area and low-power product decoder based on Improved Soft-Assisted Iterative Bounded Distance Decoding algorithm (ISA-ibdd) algorithm is presented. The ASIC synthesis results show that the proposed design leads to an 8.5 x improvement in area efficiency (AE) and a reduction of 62% in energy dissipation compared with the state-of-the-art design.
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