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An asynchronous mesh NoC based booth multiplication

IET CIRCUITS DEVICES & SYSTEMS 2019年第1期13卷 73-78页

作者： He, Anping Feng, Guangbo Zhang Jilin Wu, Jinzhao Lanzhou Univ Sch Informat Sci & Engn Lanzhou Gansu Peoples R China Lanzhou Univ Sch Phys Sci & Technol Lanzhou Gansu Peoples R China Hangzhou Dianzi Univ Coll Comp Sci Hangzhou Zhejiang Peoples R China

The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The booth structure of a multiplier is a wide-used and efficient structure of real IC systems, and the performance of a booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8-bit asynchronous booth multiplier, which is synthesized and post simulated with a Xilinx Virtex-7 FPGA development board.

关键词： arithmetic units 8-bit asynchronous booth multiplier IC system logic design multiplying circuits asynchronous mesh Xilinx Virtex-7 FPGA asynchronous circuits network-on-chip asynchronous mechanism digital arithmetic integrated logic circuits asynchronous control booth algorithm field programmable gate arrays

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Design and implementation of single electron transistor based 8X8 bit signed multipliers

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Materials Today: Proceedings 2021年 43卷 3904-3910页

作者： Chintan Shah Raj Shah Rasika Dhavse Rutu Parekh VLSI and Embedded Systems Group DA-IICT Gandhinagar India Electronics Engineering Department SVNIT Surat Gujarat 395007 India

Single electron transistor (SET) has several advantages over CMOS such as it is highly scalable and has ultra-low power consumption. It has emerged as a promising technology to be used as a building blocks for next generation integrated circuit design. In this paper, prospective and efficient implementation of high speed, low power and extremely compact digital multipliers using SET is proposed for the first time. For effective analysis and comparison, three different 8-bit signed multipliers such as Baugh Wooley, booth and Array multiplier have been designed and their simulation results are validated using the Cadence Virtuoso ADE tool. Performance comparison in terms of power and delay between SET and 16 nm CMOS is evaluated. From the simulation results, it is observed that multipliers based on SET outperforms its CMOS counterpart in all aspects. Considering above mentioned multipliers, SET based booth multiplier design is having lowest power consumption of 1.41 µW and propagation delay of 6.09 ps as compared to 7.53 µW and 454.94 ps respectively for CMOS counterpart below.

关键词： Array multiplier Baugh Wooley booth algorithm Signed multiplier Single electron transistor (SET)

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Dynamic Precision Multiplier For Deep Neural Network Accelerators 33

Dynamic Precision Multiplier For Deep Neural Network Acceler...

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33rd IEEE International System on Chip Conference (IEEE SOCC)

作者： Ding, Chen Yuxiang, Huan Zheng, Lirong Zou, Zhuo Fudan Univ Sch Informat Sci & Technol Shanghai Peoples R China

ISBN: (纸本)9781728187464

The application of dynamic precision multipliers in the deep neural network accelerators can greatly improve system's data processing capacity under same memory bandwidth limitation. This paper presents a Dynamic Precision Multiplier (DPM) for deep learning accelerators to adapt to light-weight deep learning models with varied precision. The proposed DPM adopts booth algorithm and Wallace Adder Tree to support parallel computation of signed/unsigned one 16-bit, two 8-bit or four 4-bit at run time. The DPM is further optimized with simplified partial product selection logic and mixed partial product selection structure techniques, reducing power cost for energy-efficient edge computing. The DPM is evaluated in both FPGA and ASIC flow, and the results show that 4-bit mode consumes the least energy among the three modes at 1.34pJ/word. It also saves nearly 22.38% and 232.17% of the power consumption under 16-bit and 8-bit mode respectively when comparing with previous similar designs.

关键词： dynamic precision multiplier booth algorithm mixed partial product selection structure

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Improved Multiplication algorithm by Clearing Leading Zeros of Binary Numbers based on Big Data Analysis 19

Improved Multiplication Algorithm by Clearing Leading Zeros ...

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19th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)

作者： Kim, Donghoon Jung, Jaehee Arkansas State Univ Dept Comp Sci Jonesboro AK 72401 USA Hongik Univ Dept Gen Educ Seoul South Korea

ISBN: (纸本)9781538658895

System performance plays an important role in the era of big data. As such, the multiplication algorithm and hardware have evolved to improve system performance which can support a fast big data analysis engine. Several variations on conventional booth multiplication algorithm have improved performance. However, we have observed that the existing multiplication algorithms repeating addition and shift operations conduct unnecessary iteration due to leading zeros in binary numbers. We have found that we can reduce the number of iterations by clearing unnecessary leading zeros in the multiplier. Thus, we propose two approaches to clear unnecessary leading 0s: (1) pre-front-based: pre-clearing leading zeros with the front-based multiplication algorithm and (2) post-booth: post-clearing leading zeros with the rear-based multiplication algorithm using booth algorithm. We evaluate performance with the data extracted from sparse matrices in UF Matrix Collection. Our algorithms outperform conventional multiplication algorithms by using a minimum number of necessary binary digits in the multiplier. The algorithms can be applied directly below the level of multiplication instructions with a minimal change to deal with big data ingestion.

关键词： Binary multiplication big data booth algorithm clock cycle matrix multiplication IEEE 754 floating-point

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Evaluative Comparator Hardware Implementation for State-of-the-Art High Performance Multipliers 11

Evaluative Comparator Hardware Implementation for State-of-t...

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11th UKSim-AMSS European Modelling Symposium on Computer Modelling and Simulation (EMS)

作者： Chari, Rithika Shyam Elarabi, Tarek Penn State Univ Elect & Comp Engn Dept University Pk PA 16802 USA Penn State Univ Sch Engn University Pk PA 16802 USA

ISBN: (纸本)9781538614105

The multiplier undoubtedly is one of the most critical digital logic components in computer architecture. To achieve a faster response from a system, digital logic components need to respond faster with negligible error rates. Important factors in the consideration for implementing high performance/ speed multipliers are reduction in time delay, power at maximum speed and power delay product. This paper implements and compares high performance multipliers using various algorithms and techniques. It also analyzes the performance of 2, 4 & 8-bit multipliers based on Vedic algorithm and 4 & 8-bit multipliers based on the Modified booth algorithm, and Wallace Tree. The conclusion on the most preferred choice of algorithm across the product dimension is made based on the maximum delay. The multiplier algorithms minimize the delay by reducing the number of partial products. Implementation and analysis of the results have been carried out using Verilog on Xilinx Vivado IDE.

关键词： High Performance Multipliers booth algorithm Wallace Tree Vedic Urdhva Triyakbhyam Ripple Carry Adder Carry Save Adder

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Design and Implementation of area efficient 2-parallel filter on FPGA using image system

Design and Implementation of area efficient 2-parallel filte...

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International Conference on Innovative Research In Electrical Sciences (IICIRES)

作者： Phimu, L. Kholee Kumar, Manoj Natl Inst Technol Manipur Elect & Commun Engn Imphal Manipur India

ISBN: (纸本)9781538628522

Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel FIR filter are explained. Its simulation using Xilinx 14.2 are also discussed. It also presents the FPGA implementation of primary 2-parallel filter and area-efficient 2-parallel on Xilinx 14.2 Spartan 3E Starter Board XC3S500E chips and its results. Since adders are less weight in term of silicon area when compare with the multipliers, therefore multipliers are replaced by the adder to reduce area and delay of the parallel FIR filter. Xilinx ISE 14.2 is used for simulating the design of the filter.

关键词： Finite impulse response (FIR) booth algorithm Carry look-ahead adder (CLA) Look Up Table (LUT) Parallel FIR filter Very Large Scale Integration (VLSI) FPGA

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Multiplication of a Constant (2^k ± 1) and Its Fast Hardware Implementation

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第1期82卷 41-53页

作者： Jui, Pin-Chang Wey, Chin-Long Shiue, Muh-Tian Natl Cent Univ Dept Elect Engn Jhongli Taiwan Natl Chiao Tung Univ Dept Elect & Comp Engn Hsinchu Taiwan

Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2(k) +/- 1), or (2(k) +/- 1)N, operation with additions. No multiplications are needed. The value of (2(k) +/- 1)N can be computed by adding (+/- N) to its k-bits left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure.

关键词： Constant multiplier Ripple Carry Adder (RCA) Carry-Lookahead Adder(CLA) Hybrid Adder(HyA) booth algorithm

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Self-Timed Multiplier for Multiply-Add Unit

Self-Timed Multiplier for Multiply-Add Unit

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IEEE North-West-Russia-Section Young Researchers in Electrical and Electronic Engineering Conference (ElConRusNW)

作者： Stepanov, B. Diachenko, Y. Rogdestvenski, Y. Diachenko, D. Russian Acad Sci Inst Informat Problems Fed Res Ctr Comp Sci & Control IIP RAS Moscow Russia

ISBN: (纸本)9781509004454

Paper discusses the peculiarities of self-timed multiplier implementation for unit multiplying two operands and then adding the product to third operand without an intermediate rounding according to the IEEE 754 Standard. The multiplier is a hardware implementation of modified booth algorithm on a base of self-timed adder with redundant signal code. An optimal self-timed redundant coding of internal and output signals in the multiplier was proposed. The circuitry and layout problems were solved for self-timed multiplier implementation. Wallace tree structure, which is the main part of the multiplier, was optimized for the facilities of 65-nm CMOS process with six metal layers taking into account more number of signals in the multiplier circuit, than in the synchronous analog. A release of the self-timed multiplier implementation in CMOS process with 65-nm design rules is introduced.

关键词： booth algorithm self-timed multiplier ternary coding ternary Wallace tree layout

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A Fastest Multiplier Using Two's Compliment Method

A Fastest Multiplier Using Two's Compliment Method

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International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)

作者： Srihari, C. Gantala, Anil Shruthi, L. Sravana, J. Reddy, R. Gangadhar Inst Aeronaut Engn Dept Elect & Commun Engn Hyderabad Telangana India

ISBN: (纸本)9781467399395

This paper focuses Two's complement multipliers with Shortest Bit-size were used without any increase in the delay of the partial product stage. This was done by reducing one row the maximum height of the partial product array generated by a radix-4 Modified booth multiplier, this reduction may allow for a faster compression of the partial product array and regular layout. By using this method, it will reduce the Computation Time in Two's Complement multipliers by Short Bit-Width (size) concept. This method is general and can be extended to higher radix encoding, as well as to any size square and m x n rectangular multipliers.

关键词： Multiplication booth algorithm Partial Product Array Modified booth Encoding

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Delay Efficient Error Detection and Correction of Parallel IIR Filters using VLSI algorithms

Delay Efficient Error Detection and Correction of Parallel I...

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IEEE International Conference on Emerging Technological Trends in Computing, Communications and Electrical Engineering (ICETT)

作者： Abraham, Ani Manuel, Manju Rajiv Gandhi Inst Technol Kottayam 686501 Kerala India

ISBN: (纸本)9781509037513

Almost all electronic systems suffer from errors caused by various internal and external factors. In many designs automatic detection and correction of errors is of prime importance. In the meantime the techniques that add to detect and correct errors will make the system more sluggish. This paper proposes a method for error detection and correction in parallel IIR filters based on error correction codes. Even though a lot of studies have been done with FIR filters, the area of IIR filters have received very less attention. The reason for this is design of an IIR filter is much complicated than an FIR filter due to its recursive nature. Scaling and roundoff error plays a major role and special care must be taken to overcome this. To improve the speed of the system, the conventional adders and multipliers are replaced with carry select adder and booth multiplier. The effectiveness of the scheme is shown in terms of error protection, hardware utilization and delay. A remarkable reduction in delay is obtained through the application of these algorithms.

关键词： Error correction codes (ECCs) Parallel filters Carry Select Adder booth algorithm Delay efficiency

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