Designing of a reliable digital system is a challenging task because it incorporates testing of circuits at the design time. With this feature the designer can depict testable circuit for transient faults at the desig...
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ISBN:
(纸本)9781479939145
Designing of a reliable digital system is a challenging task because it incorporates testing of circuits at the design time. With this feature the designer can depict testable circuit for transient faults at the design stage. In this paper we have proposed a technique of transient fault injection system with the help of Verilog description based language. The key feature of the fault injection system is pseudo random sequence which is generated through LFSR. Standard LFSR based fault injection system is less efficient in terms of hardware utilization;to reduce hardware of the injection system berlekamp-masseyalgorithm (BMA) is used. Experimental results show that the proposed technique has a superior performance, compared to existing technique.
With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the berlekampmassey Decoding algorithm can be modified and mapp...
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With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the berlekampmassey Decoding algorithm can be modified and mapped to obtain a low-power architecture. In addition, architecture level modifications that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low-power/high-speed decoder is presented, The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction when compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1,34.
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