The berlekamp-massey algorithm (further, the BMA) is interpreted as an algorithm for constructing Pade approximations to the Laurent series over an arbitrary field with singularity at infinity. It is shown that the BM...
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The berlekamp-massey algorithm (further, the BMA) is interpreted as an algorithm for constructing Pade approximations to the Laurent series over an arbitrary field with singularity at infinity. It is shown that the BMA is an iterative procedure for constructing the sequence of polynomials Orthogonal to the corresponding space of polynomials with respect to the inner product determined by the given series. The BMA is used to expand the exponential in continued fractions and calculate its Pade approximations.
We propose a slight modification of the berlekamp-massey algorithm for obtaining the minimal polynomial of a given linearly recurrent sequence. Such a modification enables to explain it in a simpler way and to adapt i...
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We propose a slight modification of the berlekamp-massey algorithm for obtaining the minimal polynomial of a given linearly recurrent sequence. Such a modification enables to explain it in a simpler way and to adapt it to lazy evaluation.
In this work, a new method to design a mixed-mode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by berlekamp-massey algo...
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In this work, a new method to design a mixed-mode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by berlekamp-massey algorithm (BMA) and is capable of generating pre-computed deterministic test patterns which detect the hard-to-detect faults of the circuit. Moreover, the LFSR generates residual patterns which are sufficient to detect the remaining easy-to-detect faults. In this way, the BMA-designed LFSR is a mixed-mode TPG which achieves total fault coverage with short testing length and low hardware overhead compared with previous schemes according to the experimental results.
We obtain a parallel berlekamp-massey-type algorithm for determining error locating functions for the class of one point algebraic-geometric codes. The proposed algorithm has a regular and simple structure and is suit...
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We obtain a parallel berlekamp-massey-type algorithm for determining error locating functions for the class of one point algebraic-geometric codes. The proposed algorithm has a regular and simple structure and is suitable for VLSI implementation. We give an outline for an implementation, which uses as main blocks gamma copies of a modified one-dimensional berlekamp-massey algorithm, where gamma is the order of the first nongap in the function space associated with the code. Such a parallel implementation determines the error locator for an algebraic-geometric code using the same time requirements as the underlying one-dimensional berlekamp-massey algorithm applied to the decoding of Reed-Solomon codes.
In this paper, an algebraic decoding method is proposed for the quadratic residue codes that utilize the berlekamp-massey algorithm. By a modification of the technique developed by He et al., one can express the unkno...
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In this paper, an algebraic decoding method is proposed for the quadratic residue codes that utilize the berlekamp-massey algorithm. By a modification of the technique developed by He et al., one can express the unknown syndromes as functions of the known syndromes. The unknown syndromes are determined by an efficient algorithm also developed in this paper. With the appearance of unknown syndromes, one obtains the consecutive syndromes that are needed for the application of the berlekamp-massey algorithm. The decoding scheme, developed here, is easier to implement than the previous decoding algorithm developed for the Golay code and the (47, 24, 11) QR code. Moreover, it can be extended to decode all codes of the family of binary quadratic residue codes with irreducible generating polynomials.
This paper presents a novel area-efficient key equation solver (KES) architecture for the syndrome-based Reed-Solomon (RS) decoders. We develop the compensated simplified reformulated inversionless berlekamp-massey (C...
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This paper presents a novel area-efficient key equation solver (KES) architecture for the syndrome-based Reed-Solomon (RS) decoders. We develop the compensated simplified reformulated inversionless berlekamp-massey (CS-RiBM) algorithm, which is proved to successfully remove unnecessary computations in the conventional reformulated inversionless berlekamp-massey (RiBM) algorithm with simple compensation. The proposed algorithm results in a simplified KES architecture using much fewer processing elements and can be implemented by a homogenous systolic architecture. The RS (255, 239) and RS (255, 223) decoders using the CS-RiBM architecture have been designed and synthesized with SMIC 0.18 mu m CMOS technology library. The synthesis results, excluding FIFO stacks, show that the CS-RiBM architecture can reduce 14 to 29 % area compared with the prior related architectures based on the berlekamp-massey (BM) and modified Euclidean (ME) algorithms. The proposed RS decoders achieve similarly high throughput to the RS decoders using the RiBM architecture with lower hardware complexity and are 17 to 22 % more efficient. Higher efficiency is achievable as the error-correcting capability of the RS code increases.
Real number block codes derived from the discrete Fourier transform (DFT) are corrected by coupling a very modified berlekamp-massey (BM) algorithm with a syndrome extension process. The modified BM algorithm determin...
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Real number block codes derived from the discrete Fourier transform (DFT) are corrected by coupling a very modified berlekamp-massey (BM) algorithm with a syndrome extension process. The modified BM algorithm determines recursively the locations of any large errors whose number is within the capability of the DFT code. It evolves a connection polynomial which is changed when a discrepancy is above a threshold which is adjusted during each iteration. The large error locations are repositioned to exact location indices to combat low-level noise effects. The syndromes are extended using the refined connection polynomial taps. Alternately, enhanced extension recursions based on Kalman syndrome extensions are developed and simulated.
In this paper, we adopt a restricted Gaussian elimination on the Hankel structured augmented syndrome matrix -to reinterpret an early-stopped version of the berlekamp-massey algorithm in which only (t + e) iterations ...
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In this paper, we adopt a restricted Gaussian elimination on the Hankel structured augmented syndrome matrix -to reinterpret an early-stopped version of the berlekamp-massey algorithm in which only (t + e) iterations are needed to be performed for the decoding of BCH codes up to t errors, where e is the number of errors actually occurred with e <= t, instead of the 2t iterations required in the conventional berlekamp-massey algorithm. The minimality of (t + e) iterations in this early-stopped berlekamp-massey (ESBM) algorithm is justified and related to the subject of simultaneous error correction and detection in this paper. We show that the multiplicative complexity of the ESBM algorithm is upper bounded by (te + e(2) - 1) for all e <= t and except for a trivial case, the ESBM algorithm is the most efficient algorithm for finding the error-locator polynomial.
This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless berlekamp-massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this ...
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This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless berlekamp-massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GE) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.
The berlekamp-massey algorithm finds the shortest linear feedback shift register for a binary input sequence. A wide range of applications like cryptography and digital signal processing use this algorithm. This resea...
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The berlekamp-massey algorithm finds the shortest linear feedback shift register for a binary input sequence. A wide range of applications like cryptography and digital signal processing use this algorithm. This research proposes novel parallel mechanisms offered by heterogeneous CPU and GPU hardwares in order to achieve the best possible performance for BMA. The proposed bitwise implementation of the BMA algorithm is almost 35 times faster than state of the art implementations. This further improvement is achieved by using SIMD instructions which provides data level parallelism. This new approach can be 4.6 and 35 times faster than a bitwise CPU and state of the art implementations, respectively. In order to achieve the highest possible speedup over a multi-core structure, a multi-threading implementation is introduced in this research. By leveraging on OpenMP we were able to obtain a speedup of 10 times over 12 cores server. The GPU device with thousands of processing cores can bring great speedup over the best CPU implementation. Two other parallel mechanisms offered by GPU are concurrent kernel execution and streaming. They achieve 14.5 and 2.2 times of speedup compared to CPU serial and typical CUDA implementations, respectively. Also, the performance of the openMP code with SIMD instructions is compared with GPU stream implementation. The effectiveness of the proposed method is evaluated in a real world error correction application and it achieves 6.8 times of speedup.
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