检索结果-内蒙古大学图书馆

Proceedings of the Third International Conference on AI-ML Systems

作者： Jayeeta Mondal Swarnava Dey Arijit Mukherjee Embedded Devices & Intelligent Systems TCS Research IN Embedded Devices & Intelligent Systems TCS Research Tata Consultancy Services Ltd. IN

ISBN: (纸本)9798400716492

Vision-based hand gesture recognition in human-computer interface design has useful applications in virtual-reality, gaming control, communication through sign language, medical rehabilitation etc. In many scenarios, such applications are deployed on small handheld or wearable devices, i.e. edge devices. To mitigate the challenges in building a real-time convolutional neural network (CNN) based solution at edge, researchers explore various methods to reduce the computational overhead during inference. One recent development is binarization of CNNs that replaces floating point MAC operations in a network with efficient XNOR-bit count operations, thus drastically reducing inference latency, memory and network computations. In this paper, we propose a binary convolutional neural network (BCNN) based Deep Learning (DL) inference pipeline for gesture recognition in a car infotainment system. Our DL pipeline requires 3.6x less storage space, 2.3x less network operations, and gives 3x inference speed-up compared to state-of-the-art MediaPipe gesture recognition system by Google. We observe that directly binarizing a CNN results in a large accuracy drop (48%) for our gesture data. To reduce this gap, we propose an optimized BCNN that uses 20x less inference memory, provides 6.7x inference speed-up with a accuracy drop of 12% compared with full-precision CNN in edge device.

关键词： binary convolutional neural network Embedded Systems Gesture Recognition bi-level optimization

来源：评论

学校读者我要写书评

暂无评论

A Lightweight Collaborative Recognition System with binary convolutional neural network for Mobile Web Augmented Reality 39

A Lightweight Collaborative Recognition System with Binary C...

引用

39th IEEE International Conference on Distributed Computing Systems (ICDCS)

作者： Huang, Yakun Qiao, Xiuquan Ren, Pei Liu, Ling Pu, Calton Chen, Junliang Beijing Univ Posts & Telecommun Beijing Peoples R China Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781728125190

Lightweight and precise recognition is a key component of web-based augmented reality (Web AR) applications. Although edge-based distributed deep learning approach is now possible to achieve satisfactory recognition for Web AR applications, it puts significant pressure on the computation and energy consumption of the mobile web browser, especially the app-based embedded browser. Thus, reducing the model size and accelerating the inference are regarded as the two fundamental challenges to enable this edge-based collaborative recognition system efficiently. In this paper, we propose a lightweight collaborative recognition system (LCRS) for Web AR applications. LCRS contributes to three aspects: (1) we design a composite deep neural network for reducing the model size and inference latency by introducing binary convolutional neural network;(2) we provide a joint training method to co-train the general branch and the binary branch;(3) we develop a JavaScript library for the mobile web browser to execute and accelerate inference of the binary branch, which also provides a collaborative mechanism between the mobile web browser and the edge server. We have conducted extensive experiments using several well-known networks and datasets. The experimental results have shown that the proposed system outperforms the existing approaches in terms of reducing the model size by about 16x to 29x, and it also reduces end-to-end latency and outpaces the existing state-of-the-art approaches by over 3x to 60x when applying it in practical Web AR cases.

关键词： Distributed deep neural networks binary convolutional neural network mobile computing edge computing web augmented reality

来源：评论

学校读者我要写书评

暂无评论

Modulated binary Clique convolutional neural network 7

Modulated Binary Clique Convolutional Neural Network

引用

7th International Conference on Advanced Cloud and Big Data (CBD)

作者： Xia, Jinpeng Wu, Jiasong Wu, Fuzhi Kong, Youyong Zhang, Pinzheng Senhadji, Lotfi Shu, Huazhong Southeast Univ Minist Educ Key Lab Comp Network & Informati Integrat Nanjing Peoples R China Univ Rennes 1 Ctr Rech Informat Med Sinofrancais CRIBs LTSI INSERMU1099 Rennes France

ISBN: (纸本)9781728151410

Although convolutional neural networks (CNNs) achieve effectiveness in various computer vision tasks, the significant requirement of storage of such networks hinders the deployment on computationally limited devices. In this paper, we propose a new compact and portable deep learning network named Modulated binary Clique convolutional neural network (MBCliqueNet) aiming to improve the portability of CNNs based on binarized filters while achieving comparable performance with the full-precision CNNs like Resnet. In MBCliqueNet, we introduce a novel modulated operation to approximate the unbinarized filters and gives an initialization method to speed up its convergence. We reduce the extra parameters caused by modulated operation with parameters sharing. As a result, the proposed MBCliqueNet can reduce the required storage space of convolutional filters by a factor of at least 32, in contrast to the full-precision model, and achieve better performance than other state-of-the-art binarized models. More importantly, our model compares even better with some full-precision models like Resnet on the dataset we used.

关键词： deep learning modulate process binary convolutional neural network MBCliqueNet

来源：评论

学校读者我要写书评

暂无评论

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

引用

JAPANESE JOURNAL OF APPLIED PHYSICS 2022年第SC期61卷 SC1083-SC1083页

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Univ Aizu Kami Iawase 90 Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ Aoba Ku 2-1-1 Katahira Sendai Miyagi 9808577 Japan

A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.

关键词： Field-Programmable Gate Array Lookup Table Nonvolatile Magnetic Tunnel Junction Spin-Orbit Torque binary convolutional neural network

来源：评论

学校读者我要写书评

暂无评论

Efficient binary 3D convolutional neural network and hardware accelerator

引用

JOURNAL OF REAL-TIME IMAGE PROCESSING 2022年第1期19卷 61-71页

作者： Li, Guoqing Zhang, Meng Zhang, Qianru Lin, Zhijian Southeast Univ Sch Elect Sci & Engn Natl ASIC Res Ctr Nanjing 210096 Peoples R China Southeast Univ Sch Microelect Nanjing 210096 Peoples R China

The three-dimensional convolutional neural networks have abundant parameters and computational costs. It is urgent to compress the three-dimensional convolutional neural network. In this paper, an efficient and simple binary three-dimensional convolutional neural network architecture is proposed, in which the weight and activation are constrained to 0 or 1 instead of the common + 1 or - 1. binary weight and activation are first applied to the three-dimensional convolutional neural networks. The proposed binary three-dimensional convolutional neural network has less computational complexity and memory consumption than standard convolution, and it is more appropriate for digital hardware design. Furthermore, an optimized convolution operation is proposed, in which case one input pixel is only required to be read once. A distributed storage approach is proposed to support the proposed convolution operation. With the proposed methods, a hardware accelerator for the binary three-dimensional convolutional neural network on the field programmable gate array platform is designed. The experimental results show that the presented accelerator is excellent in terms of computational resources and power efficiency. By jointly optimizing the algorithm and hardware, the accelerator achieves 89.2% accuracy and 384 frames per second on the KTH dataset.

关键词： binary convolutional neural network Hardware accelerator Three-dimensional convolution Action recognition FPGA

来源：评论

学校读者我要写书评

暂无评论

binary Single-dimensional convolutional neural network for Seizure Prediction 52

Binary Single-dimensional Convolutional Neural Network for S...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Zhao, Shiqi Yang, Jie Xu, Yankun Sawan, Mohamad Zhejiang Univ Hangzhou 310058 Zhejiang Peoples R China Westlake Univ Sch Engn CenBRAIN Lab Hangzhou 310024 Zhejiang Peoples R China

ISBN: (纸本)9781728133201

Nowadays, several deep learning methods are proposed to tackle the challenge of epileptic seizure prediction. However, these methods still cannot be implemented as part of implantable or efficient wearable devices due to their large hardware and corresponding high-power consumption. They usually require complex feature extraction process, large memory for storing high precision parameters and complex arithmetic computation, which greatly increases required hardware resources. Moreover, available yield poor prediction performance, because they adopt network architecture directly from image recognition applications fails to accurately consider the characteristics of EEG signals. We propose in this paper a hardware-friendly network called binary Single-dimensional convolutional neural network (BSDCNN) intended for epileptic seizure prediction. BSDCNN utilizes 1D convolutional kernels to improve prediction performance. All parameters are binarized to reduce the required computation and storage, except the first layer. Overall area under curve, sensitivity, and false prediction rate reaches 0.915, 89.26%, 0.117/h and 0.970, 94.69%, 0.095/h on American Epilepsy Society Seizure Prediction Challenge (AES) dataset and the CHB-MIT one respectively. The proposed architecture outperforms recent works while offering 7.2 and 25.5 times reductions on the size of parameter and computation, respectively.

关键词： seizure prediction electroencephalography (EEG) deep learning single-dimensional convolution binary convolutional neural network hardware-friendly

来源：评论

学校读者我要写书评

暂无评论

Design of a Nonvolatile-neural-network-Accelerator-Embedded Edge-IoT Device and Its Hardware Emulation 16

Design of a Nonvolatile-Neural-Network-Accelerator-Embedded ...

引用

16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

作者： Sato, Ken Suzuki, Daisuke Univ Aizu Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9798350393613

Edge-IoT device with AI accelerator has advantages such as increased processing speed and more robust security, however, it has disadvantages such as limited resources and high power consumption during standby state caused by leakage current to retain internal data. To solve this issue, a nonvolatile-logic-based edge-IoT device which includes not only a nonvolatile AI accelerator but also a power management unit (PMU) and CPU is proposed and its functional behavior is emulated on a field-programmable gate array (FPGA). The use of the nonvolatile AI accelerator makes it possible to shorten the inference time and immediately fall into a power-off state without losing internal data, which results in great energy saving. The combination of the CPU with the PMU makes it possible to perform software-level management of the operation and power supply for the AI accelerator. As a typical design example, the proposed edge-IoT device which includes a binary convolutional neural network (BCNN) accelerator for digit recognition is designed and its function is emulated on a Digilent Basys3 FPGA board. The estimation result shows that the total energy for the periodical inference (1 image per 100 mu s) of the proposed edge-IoT device is reduced by 92% compared to that of a volatile edge-IoT device with a slight hardware overhead.

关键词： Nonvolatile logic FPGA binary convolutional neural network IoT Edge computing

来源：评论

学校读者我要写书评

暂无评论

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

引用

JAPANESE JOURNAL OF APPLIED PHYSICS 2021年第SB期60卷

作者： Suzuki, Daisuke Oka, Takahiro Hanyu, Takahiro Univ Aizu Kami Iawase 90 Aizu Wakamatsu Fukushima 9658580 Japan Tohoku Univ Aoba Ku 2-1-1 Katahira Sendai Miyagi 9808577 Japan

This paper presents an energy-efficient hardware accelerator for binarized convolutional neural networks (BCNNs). In this BCNN accelerator, a data-shift operation becomes dominant to effectively control input/weight-data streams under limited memory bandwidth. A magnetic-tunnel-junction (MTJ)-based nonvolatile field-programmable gate array (NV-FPGA), where the amount of stored-data updating is minimized in a configurable logic block, is a well-suited hardware platform for implementing such a BCNN accelerator. Owing to the nonvolatile storage capability of the NV-FPGA, not only power consumption in the data-shift operation but also standby power consumption in the idle function block is reduced without losing internal data. It is demonstrated under 45 nm complementary metal-oxide-semiconductor/MTJ process technologies that the energy consumption of the proposed BCNN accelerator is 50.7% lower than that of a BCNN accelerator using a conventional static-random-access-memory-based FPGA.

关键词： FPGA binary convolutional neural network Nonvolatile Lookup Table Circuit Magnetic Tunnel Junction Edge-AI

来源：评论

学校读者我要写书评

暂无评论

A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating binary neural networks 38

A PVT-robust Customized 4T Embedded DRAM Cell Array for Acce...

引用

38th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Shin, Hyein Sim, Jaehyeong Lee, Daewoong Kim, Lee-Sup Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781728123509

Deep neural networks (DNNs) are widely used for real-world applications. However, large amount of kernel and intermediate data incur a memory wall problem in resource-limited edge devices. The recent advances of a binary deep neural network (BNN) and a computing in-memory (CIM) have effectively alleviated this bottleneck especially when they are combined together. However, previous CIM-based accelerators for BNN are highly vulnerable to process/supply voltage/temperature (PVT) variation, resulting in severe accuracy degradation which makes them impractical to be employed in real-world edge devices. To address this vulnerability, we propose a PVT-robust accelerator architecture for BNN with a computable 4T embedded DRAM (eDRAM) cell array. First, we implement the XNOR operation of BNN in a time-multiplexed manner by utilizing the fundamental read operation of the conventional eDRAM cell. Next, a PVT-robust bit-count based on charge sharing is proposed with a computable 4T eDRAM cell array. In result, the proposed architecture achieves 6.9x less variation in PVT-variant environments which guarantees a stable accuracy and 2.03-49.4x improvement of energy efficiency over previous CIM-based accelerators.

关键词： Processing in-memory binary convolutional neural network eDRAM

来源：评论

学校读者我要写书评

暂无评论

FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-based Memory Array 37

FeMAT: Exploring In-Memory Processing in Multifunctional FeF...

引用

37th IEEE International Conference on Computer Design (ICCD)

作者： Zhang, Xiaoyu Chen, Xiaoming Han, Yinhe Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781538666487

The performance gap between the processors and the main memory is continuously widening, known as the memory wall bottleneck. Emerging nonvolatile devices have the ability of in-memory processing, and thus, have the potential to partially alleviate the memory wall bottleneck. People have adopted nonvolatile devices to build various accelerators that are targeted at different problems and applications. In this work, we adopt one of the emerging nonvolatile devices, the ferroelectric field-effect transistor (FeFET), to build a multi-functional in-memory processing unit, which is named FeMAT. From a structural point of view, FeMAT is an FeFET-based memory array composed of 3T-based cells. From a functional point of view, FeMAT not only is a nonvolatile memory, but also can perform some logic operations (i.e., the processing-in-memory (PIM) mode), binary convolutions (i.e., the binary convolutional neural network (BCNN) acceleration mode) and content searching (i.e., the ternary content-addressable memory (TCAM) mode) in the memory. These functions are seamlessly fused into the FeFET-based memory array and can be configured online without changing the circuit structure. Superior energy efficiency is demonstrated by our experiments and comparisons with a resistive random-access memory (ReRAM) based equivalence, as well as a TCAM and a BCNN accelerator based on complementary metal-oxide-semiconductor (CMOS) devices.

关键词： Ferroelectric field-effect transistor in-memory processing ternary content-addressable memory binary convolutional neural network

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：