In this paper, the discontinuous meshes are applied to CAE analysis. Besides that, a dual interpolation boundary face method based on the Hermite-type moving-least-squares method (DiBFM-HMLS) for the 3D elasticity pro...
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In this paper, the discontinuous meshes are applied to CAE analysis. Besides that, a dual interpolation boundary face method based on the Hermite-type moving-least-squares method (DiBFM-HMLS) for the 3D elasticity problem is firstly proposed. The DiBFM-HMLS offers an interpolation scheme for the hang points in the discontinuous meshes. Different from the previous mesh division method, the binary-tree structure is used to obtain the discontinuous meshes. Our mesh generation method can effectively avoid model repairing and simplification for geometric structures with small features and defects while ensuring a real automatic mesh division. Compared with the continuous mesh, the discontinuous meshes possess strong geometric adaptability for arbitrarily complicated structures and can provide the possibility for the full-automatic CAE analysis. Suc-cessful numerical examples are used to illustrate the accuracy and reliability of the presented methods in solving various kinds of problems and reveal the excellent performance of the discontinuous meshes.
Due to the simplicity of scheduling, the buffered crossbar is becoming attractive for high-speed communication system. Although the previously proposed Round-Robin algorithms achieve 100% throughput under uniform traf...
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ISBN:
(纸本)9781457706608
Due to the simplicity of scheduling, the buffered crossbar is becoming attractive for high-speed communication system. Although the previously proposed Round-Robin algorithms achieve 100% throughput under uniform traffic, they can not achieve a satisfactory performance under non-uniform traffic. In this paper, we propose an efficient Round-Robin scheduling algorithm based on binary-tree scheme where service policy is applied to improve Quality-of-Service. With the proposed scheduling algorithm, the searching time-complexity of O(1) (one clock cycle) and 100% throughput under non-uniform traffic can be obtained. Based on a binary-tree structure, the design achieves high-speed data rate at Tbps, and simpler design with combinational circuits. The design has been simulated on both FPGA-based (Virtex 5) and Silicon-based technology (0.18 um). The synthesis results show that consumed resources varied from 11 to 533 slices and from 46 to 1686 2-NAND gates for crossbars of size 4x4 to 128x128. Critical path delays from 0.72 to 4.52 ns for FPGA-based and from 1.33 to 4.0 ns for silicon-based have obtained for the design.
The N-input multiplexers based on CMOS switches are conventionally designed with the binarytreestructure to simplify the address decoder and obtain a reasonable delay, which estimates the propagation time from data ...
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The N-input multiplexers based on CMOS switches are conventionally designed with the binarytreestructure to simplify the address decoder and obtain a reasonable delay, which estimates the propagation time from data input end to the output end of the multiplexers. However, this design strategy in general takes too much hardware and incurs too much delay. To reduce both delay and cost, some structures other than the binary-tree structure have to be used. Therefore, in this paper we propose a general procedure based on the heterogeneous-treestructure for designing fast large fan-in CMOS multiplexers. The results show that not only can the speed be increased but the cost can also be reduced considerably for the proposed circuits with various input sizes. In addition, we show that both the binary-tree structure and the uniform structure are special cases of the proposed approach.
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