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High performance word level sequential and parallel coding methods and architectures for bit plane coding

Science in China(Series F) 2008年第4期51卷 337-351页

作者： XIONG ChengYi TIAN JinWen LIU Jian College of Electronic Information Engineering South-Central University for Nationalities Wuhan 430074 China Institute of Pattern Recognition & Artificial Intelligence Key Laboratory of Education Ministry for Image Processing and Intelligent Control Huazhong University of Science & Technology Wuhan 430074 China

This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.

关键词： bit plane coding high performance word-level sequential multi-word parallel

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High Speed and Memory Efficient Parallel bit plane coding Architecture for JPEG2000

High Speed and Memory Efficient Parallel Bit Plane Coding Ar...

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6th Indian Conference on Computer Vision, Graphics and Image Processing

作者： Suman, Tenugu Chatterjee, Sumit Kumar Chakrabarti, Indrajit Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781424442195

bit plane coding (BPC) constitutes an important component of the EBCOT Tier-1 block of JPEG2000 encoder. This paper proposes an efficient parallel hardware structure to implement the computation intensive word level bit plane coding algorithm. The proposed architecture computes the context and decision for all bit planes in parallel. The three coding passes are merged for all bit planes in a scan while the samples are coded in sequence. The proposed parallel BPC architecture offers a speed of 31 over the serial BPC architecture. Its memory requirement is independent of the size of the codeblock. The speed of the proposed architecture has been shown to be significantly faster than an architecture which has been recently reported in literature. The system architecture has been functionally verified by ModelSim and synthesized by TSMC 0.25 mu m vtvt CMOS cell libraries.

关键词： bit plane coding JPEG2000 encoder codeblock parallel architecture

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High speed multiple word parallel architecture for bit plane coding used in JPEG 2000

High speed multiple word parallel architecture for bit plane...

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5th International Conference on Machine Learning and Cybernetics

作者： Xiong, Cheng-Yi Hou, Jian-Hua He, Xiang South Ctr Univ Natl Coll Elect Informat Engn Wuhan 430074 Peoples R China

ISBN: (纸本)1424400600

This paper presented a high speed multiple word parallel architecture (MWPA) with sequential coding for fractional bit plane coding used in JPEG 2000, where all bit planes are coded in parallel, and all bit samples in the same bit plane are coded in sequential. The proposed MWPA adopts a technique of performing the coding pass prediction and context formation in parallel and pipelined fashion, thus context formation for a column of 4 coefficients could be achieved in each intra-clock cycle, and multiple passes coding of fractional bit plane coding are completed by one scan. Theoretical analysis and experimental results demonstrate that, the proposed MWPA could significantly increase throughput rate with good performance in terms of speedup to cost, compared with the previous works.

关键词： JPEG 2000 bit plane coding high speed VLSI architecture parallel pipeline sequential

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Novel word-level sequential scheme and parallel architecture for bit plane coding in JPEG2000

Novel word-level sequential scheme and parallel architecture...

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8th International Conference on Signal Processing

作者： Gao, Zhirong Xiong, Chengyi Wuhan Univ Sci & Technol Dept Comp Sci Wuhan 430074 Peoples R China South Ctr Univ Nationalities Coll Elect Informat Engn Wuhan 430074 Peoples R China

ISBN: (纸本)9780780397361

This paper presented an improved word-level sequential scheme and parallel architecture for bit plane coding of EBCOT used in JPEG 2000. The bit plane coding adopted by EBCOT is divided into two stages: coding pass prediction and context formation, which work in parallel and pipelined. Word-level and sequential bit plane coding could be achieved that coefficient bits modelling in different bit plane are performed concurrently and, all three passes coding included in each bit plane are completed in one scan. Experimental result demonstrates that the proposed architecture could efficiently reduce hardware complexity, compared to the up-to-date design.

关键词： bit plane coding word-level sequential pipeline parallel

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HIGH SPEED MULTIPLE WORD PARALLEL ARCHITECTURE FOR bit plane coding USED IN JPEG 2000

HIGH SPEED MULTIPLE WORD PARALLEL ARCHITECTURE FOR BIT PLANE...

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2006 International Conference on Machine Learning and Cybernetics(IEEE第五届机器学习与控制论坛)

作者： CHENG-YI XIONG JIAN-HUA HOU XIANG HE College of Electronic Information Engineering South-Center University for Nationalities Wuhan 430074 China

关键词： JPEG 2000 bit plane coding high speed VLSI architecture parallel pipeline sequential

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Novel Word-Level Sequential Scheme and Parallel Architecture For bit plane coding in JPEG2000

Novel Word-Level Sequential Scheme and Parallel Architecture...

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2006 8th International Conference on Signal Processing

作者： Zhirong Gao Chengyi Xiong Department of Computer Science Wuhan University of Science & Engineering College of Electronic Information Engineering South-Center University for Nationalities

This paper presented an improved word -level sequential scheme and parallel architecture for bit plane coding of EBCOT used in JPEG *** bit plane coding adopted by EBCOT is divided into two stages:coding pass prediction and context formation,which work in parallel and pipelined. Word-level and sequential bit plane coding could be achieved that coefficient bits modelling in different bit plane are performed concurrently and,all three passes coding included in each bit plane are completed in one *** result demonstrates that the proposed architecture could efficiently reduce hardware complexity,compared to the up-to -date design.

关键词： bit plane coding word-level sequential pipeline parallel.

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bit-plane coding in Extractable Source coding: Optimality, Modeling, and Application to 360° Data

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IEEE COMMUNICATIONS LETTERS 2021年第5期25卷 1412-1416页

作者： Ye, Fangping Bidgoli, Navid Mahmoudian Dupraz, Elsa Roumy, Aline Amis, Karine Maugey, Thomas UBL Lab STICC IMT Atlantique F-29238 Brest France Inria Rennes F-35042 Rennes France

In extractable source coding, multiple correlated sources are jointly compressed but can be individually accessed in the compressed domain. Performance is measured in terms of storage and transmission rates. This problem has multiple applications in interactive video compression such as Free Viewpoint Television or navigation in 360 degrees videos. In this letter, we analyze and improve a practical coding scheme. We consider a binarized coding scheme, which insures a low decoding complexity. First, we show that binarization does not impact the transmission rate but only slightly the storage with respect to a symbol based approach. Second, we propose a Q-ary symmetric model to represent the pairwise joint distribution of the sources instead of the widely used Laplacian model. Third, we introduce a novel pre-estimation strategy, which allows to infer the symbols of some bit planes without any additional data and therefore permits to reduce the storage and transmission rates. In the context of 360 degrees images, the proposed scheme allows to save 14% and 34% bitrate in storage and transmission rates respectively.

关键词： Decoding Parity check codes Source coding Laplace equations Image coding Data models Video compression Source coding with side information source modeling bit plane coding LDPC

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OFDM PEAK TO AVERAGE POWER RATIO REDUCTION USING SPARSE bit-plane coding

OFDM PEAK TO AVERAGE POWER RATIO REDUCTION USING SPARSE BIT-...

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2010 IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Sung, Cheng-Han Hu, Yu Hen Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

ISBN: (纸本)9781424442966

A novel Peak to Average Power Ratio (PAPR) reduction method leveraging the rare occurrence of large magnitude Orthogonal Frequency Division Multiplexing (OFDM) symbols is proposed. A distinct innovation of this approach is the exploitation of the sparseness structure of a bit-plane binary number representation of time domain OFDM symbols. By encoding the sparsely populated non-zero entries in the binary bit plane matrix, the dynamic range of OFDM symbols to be transmitted can be significantly reduced without increasing bit error rate. Smaller dynamic range of OFDM symbols implies reduced PAPR, and hence better performance. This method incurs no data rate reduction penalty which may occur when side information must be transmitted via some data subcarriers. Simulation results reveal that this proposed new method out-performs current PAPR reduction methods by wide margins.

关键词： OFDM Peak-to-Average-Power-Ratio (PAPR) bit plane coding sparse coding

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OFDM PEAK TO AVERAGE POWER RATIO REDUCTION USING SPARSE bit-plane coding

OFDM PEAK TO AVERAGE POWER RATIO REDUCTION USING SPARSE BIT-...

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IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Cheng-Han Sung Yu Hen Hu Department of Electrical and Computer Engineering University of Wisconsin-Madison Madison WI 53706-1691 USA

ISBN: (纸本)9781424442959

关键词： OFDM Peak-to-Average-Power-Ratio (PAPR) bit plane coding sparse coding Orthogonal frequency division multiplexing Sparse coding Peak to average power ratio Signs and symbols bit error rate Number Representation

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Lossless Compression on MRI Images Using SWT

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JOURNAL OF DIGITAL IMAGING 2014年第5期27卷 594-600页

作者： Anusuya, V. Raghavan, V. Srinivasa Kavitha, G. PSR Engn Coll Dept Comp Sci & Engn Sivakasi India Loyola Inst Technol Chennai Tamil Nadu India AAA Coll Engn & Technol Sivakasi Tamil Nadu India

Medical image compression is one of the growing research fields in biomedical applications. Most medical images need to be compressed using lossless compression as each pixel information is valuable. With the wide pervasiveness of medical imaging applications in health-care settings and the increased interest in telemedicine technologies, it has become essential to reduce both storage and transmission bandwidth requirements needed for archival and communication of related data, preferably by employing lossless compression methods. Furthermore, providing random access as well as resolution and quality scalability to the compressed data has become of great utility. Random access refers to the ability to decode any section of the compressed image without having to decode the entire data set. The system proposes to implement a lossless codec using an entropy coder. 3D medical images are decomposed into 2D slices and subjected to 2D-stationary wavelet transform (SWT). The decimated coefficients are compressed in parallel using embedded block coding with optimized truncation of the embedded bit stream. These bit streams are decoded and reconstructed using inverse SWT. Finally, the compression ratio (CR) is evaluated to prove the efficiency of the proposal. As an enhancement, the proposed system concentrates on minimizing the computation time by introducing parallel computing on the arithmetic coding stage as it deals with multiple subslices.

关键词： Stationary wavelet transform EBCOT Arithmetic coding bit plane coding

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