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Channel-Aware Gradient Descent bit-flipping algorithm for LDPC Codes

IEEE COMMUNICATIONS LETTERS 2025年第4期29卷 809-813页

作者： Min, Woohong Yang, Kyeongcheol Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang Si 37673 Gyeongsangbuk D South Korea

The gradient descent bit-flipping with momentum (GDBF-w/M) and probabilistic GDBF-w/M (PGDBF-w/M) algorithms significantly improve the decoding performance of the bit-flipping (BF) algorithm. In this letter, we propose a channel-aware GDBF-w/M algorithm which operates deterministically based on the received values from the additive white Gaussian noise (AWGN) channel. Numerical results show that the proposed algorithm does not only mitigate the error-floor phenomenon of the GDBF-w/M algorithm, but it also has better decoding performance than the PGDBF-w/M algorithm without the need for a random number generator. Furthermore, the complexity of the proposed algorithm is slightly higher than that of the GDBF-w/M algorithm.

关键词： Decoding Probabilistic logic Iterative decoding Vectors AWGN channels Indexes Training Reliability Optimization Maximum likelihood decoding LDPC codes bit-flipping algorithm decoding algorithms

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Analysis of bit-flipping algorithm of Irregular Low-Density Parity-Check Codes 11

Analysis of Bit-Flipping Algorithm of Irregular Low-Density ...

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11th International Conference on Information and Communication Technology Convergence (ICTC) - Data, Network, and AI in the age of Untact (ICTC)

作者： Kim, Myungin Ha, Jeongseok Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781728167589

In this work, we analytically derive the evolution of single-bit messages in the bit-flipping algorithm (BFA) for irregular low-density parity-check (LDPC) codes on the binary symmetric channel (BSC). In particular, the analysis tracks the probability distributions of the flipping functions and the bit-decision error at each iteration, which is possible by introducing a state variable at each variable node. The probability distributions are indirectly obtained by taking advantage of the state and state transition probabilities. The analysis will be confirmed by comparing analytic evaluations with simulation results. For the comparison, we implement LDPC codes at a finite length.

关键词： LDPC codes bit-flipping algorithm irregular degree distribution state probability state transition probability

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Density Evolution of the bit-flipping Decoding algorithm of Regular Low-Density Parity-Check Codes 10

Density Evolution of the Bit-Flipping Decoding Algorithm of ...

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10th International Conference on Information and Communication Technology Convergence (ICTC) - ICT Convergence Leading the Autonomous Future

作者： Kim, Myungin Ha, Jeongseok Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781728108933

In this paper, we develop the density evolution of bit-flipping algorithm (BFA) for regular low-density parity-check (LDPC) codes and analyze the evolution of probability density for the bit-decision error. In contrast to the sum-product algorithm (SPA) and min-sum algorithm (MSA), the density evolution for BFA has remained untouched, which motivates this work. In the developed density evolution for BFA, we first introduce a state variable which is a function of bit-decision result and the flipping function value at each iteration. Then, the state probability is derived, with which the density of bit-decision error is obtained. To confirm the derivations, we design regular LDPC codes and compare the empirical evaluations of bit-error rates and the derived probability of bit-decision errors.

关键词： LDPC code bit-flipping algorithm flipping function density evolution

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Frequency memory based gradient descent bit flipping algorithm

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IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING 2015年第5期10卷 585-591页

作者： Asatani, Jun Kawanishi, Hiroaki Tokushige, Hitoshi Katayama, Kengo Okayama Univ Sci Dept Informat & Comp Engn Fac Engn Kita Ku Okayama 7000005 Japan Kumamoto Gakuen Univ Fac Commerce Dept Commerce Chuo Ku Kumamoto 8628680 Japan

An escape method for the local optima of the gradient descent bit-flipping (GDBF) algorithm for decoding low-density parity-check codes is proposed. In the GDBF algorithm, a search point is likely to be trapped in a local optimum, which causes performance degradation of the algorithm. To address this issue, we introduce a list to store the frequency of visits to each local optimum and devise a strategy to increase the distance of a search point from a local optimum with respect to the frequency. (c) 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

关键词： bit-flipping algorithm LDPC codes combinatorial optimization problem local optima

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A Uniformly Segmented SC-Flip Decoder for Polar Codes with Memory Reduction Methods 53

A Uniformly Segmented SC-Flip Decoder for Polar Codes with M...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Lee, Useok Roh, Jae Hong Hwangbo, Chan Sunwoo, Myung Hoon Ajou Univ Dept Elect & Comp Engn Suwon South Korea

ISBN: (纸本)9781728192017

The successive cancellation flip (SCF) algorithm has been proposed to improve the error correction performance of polar codes. For hardware implementation of the SCF decoder, additional memories for storing intermediate decoding results are required not to return to the first bit during additional attempts in decoding. This paper proposes a uniformly segmented SCF decoder with memory reduction methods. We analyze the critical set distribution and uniformly segment the entire codeword to reduce the memory for storing the intermediate decoding results. The proposed decoder is implemented in Verilog HDL and synthesized using the Samsung 65 nm standard cell library. It shows 7% smaller area compared with the SC list (SCL) decoder with the list size L=2. Compared to the recent SCF decoder and fast-SSCF decoder, the proposed decoder has 34% better throughput and 23% less area respectively.

关键词： Polar codes successive-cancellation decoding bit-flipping algorithm segmentation critical set

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A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm 15

A 3.01 mm<SUP>2</SUP> 65.38Gb/s Stochastic LDPC Decoder for ...

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15th IEEE Asian Solid-State Circuits Conference (A-SSCC)

作者： Zhang, Qichen Chen, Yun Zeng, Xiaoyang Parhi, Keshab K. Nikolic, Borivoje Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Univ Minnesota Dept Elect & Comp Engn Minneapolis MN USA Univ Calif Berkeley Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781728151069

A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption;these include: variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.

关键词： Stochastic computation High throughput decoder bit-flipping algorithm

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Low-Comprexity Sliding Window Block decoding Using bit-flipping for OVFDM Systems

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IEEE ACCESS 2017年 5卷 25171-25180页

作者： Zhang, Hongtao Chen, Ying Li, Daoben Wang, Yafeng Beijing Univ Posts & Telecommun Sch Informat & Commun Engn Beijing 100876 Peoples R China

Overlapped frequency division multiplexing (OVFDM) systems can obtain high spectral effciency (SE), which is proportional to the constraint length. However, high decoding complexity imposes the main challenge on OVFDM systems. This paper proposes a low-complexity sliding window ( SW) block decoding algorithm for OVFDM systems, where data symbols are estimated based on the reception of a SW instead of a date frame. Specifically, block code of each SW is decoded by bit-flipping algorithm where the bits to be flipped are selected according to the largest absolute value criterion. Using this criterion, the complexity to obtain the near optimal bit-flipping vector grows only linearly with the SW length. In addition, the study of the decoding algorithm is based on the design of OVFDM encoding structure, where symbols can occupy orthogonal in-phase and quadrature channels simultaneously to further improve SE by a factor of two. Simulation results show that OVFDM SW decoding with bit-flipping algorithm can be used when constraint length is relatively high (constraint length >= 20) because the complexity goes roughly linearly with the increase of constraint length.

关键词： OVFDM sliding window decoding bit-flipping algorithm block code spectral efficiency

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A Modified Gradient Descent bit flipping Decoding Scheme for LDPC Codes

A Modified Gradient Descent Bit Flipping Decoding Scheme for...

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IEEE International Workshop on Signal Processing Systems (SiPS)

作者： Li, Mao-Ruei Jhuang, Li-Min Ueng, Yeong-Luh Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9781538604465

It is known that the Gradient descent bit flipping (GDBF) algorithm is an effective hard-decision decoding algorithm for low-density parity-check (LDPC) codes. However, trapping in a local maximum limits its error-rate performance. This paper presents a modified GDBF scheme that can mitigate the trapping problem and hence can improve the error-rate performance. Compared to the conventional GDBF algorithm, the proposed method is able to improve the decoding performance of 0.3dB for an (18582, 16626) code. The (18582, 16626) LDPC decoder integrates 636k logic gates and achieves a throughput of 12.4 Gbps at a clock frequency of 200 MHz in a 90nm process.

关键词： LDPC codes hard-decision decoding bit-flipping algorithm gradient descent bit-flipping (GDBF) algorithm

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On Error Correction Capability of bit-flipping algorithm for LDPC Codes

On Error Correction Capability of Bit-Flipping Algorithm for...

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IEEE International Symposium on Information Theory (ISIT)

作者： Chen, Wen-Yao Lu, Chung-Chin Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

ISBN: (纸本)9781457705953

The error correction capability of bit-flipping decoding algorithm for low density parity-check (LDPC) codes is studied by introducing variable node adjacency (VNA) graphs which are derived from Tanner graphs of LDPC codes. For codes with column weight lambda and girth g - 8, it can be shown that error patterns of weight less than or equal to lambda - 1 can be corrected. This result implies that the bit-flipping algorithm could decode up to the random error-correcting capability over binary symmetric channel for girth 8 codes whose random error-correcting capability is equal to lambda - perpendicular to.

关键词： Low density parity-check codes bit-flipping algorithm Tanner graphs variable node adjacency graphs

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Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2016年第9期63卷 873-877页

作者： Wu, Di Chen, Yun Zhang, Qichen Ueng, Yeong-luh Zeng, Xiaoyang Fudan Univ State Key Lab Applicat Specif Integrated Circuit Shanghai 200433 Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan Natl Tsing Hua Univ Inst Commun Engn Hsinchu 30013 Taiwan

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.

关键词： bit-flipping algorithm high-throughput decoder low-density parity-check (LDPC) codes stochastic decoding

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