The successive cancellation flip (SCF) algorithm has been proposed to improve the error correction performance of polar codes. For hardware implementation of the SCF decoder, additional memories for storing intermedia...
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ISBN:
(纸本)9781728192017
The successive cancellation flip (SCF) algorithm has been proposed to improve the error correction performance of polar codes. For hardware implementation of the SCF decoder, additional memories for storing intermediate decoding results are required not to return to the first bit during additional attempts in decoding. This paper proposes a uniformly segmented SCF decoder with memory reduction methods. We analyze the critical set distribution and uniformly segment the entire codeword to reduce the memory for storing the intermediate decoding results. The proposed decoder is implemented in Verilog HDL and synthesized using the Samsung 65 nm standard cell library. It shows 7% smaller area compared with the SC list (SCL) decoder with the list size L=2. Compared to the recent SCF decoder and fast-SSCF decoder, the proposed decoder has 34% better throughput and 23% less area respectively.
A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power cons...
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ISBN:
(纸本)9781728151069
A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption;these include: variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.
The reliability ratio weighted based bit-flipping (RRWBF) algorithm for decoding low-density parity-check (LDPC) codes has recently been developed to provide the best performance among all existing bit-flipping based ...
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ISBN:
(纸本)9781424428281
The reliability ratio weighted based bit-flipping (RRWBF) algorithm for decoding low-density parity-check (LDPC) codes has recently been developed to provide the best performance among all existing bit-flipping based algorithms. The implementation efficient reliability ratio weighted based bit-flipping (IERRWBF) algorithm speedup the original algorithm to decrease the processing time used. A drawback for this;algorithm is the decrease in the improvement as the maximum number of iterations assigned for the algorithm increase as a large percentage of decoding time is spent on the iteration part without any change in the performance. In this paper, a modified version for this algorithm is proposed to solve this drawback by reducing the number of iterations required to achieve the same performance of the existing IERRWBF algorithm using efficient number of iterations instead of using the maximum number of iterations for decoding without any change in the performance of the IERRWBF.
Low density parity check (LDPC) codes are one of the error-correction codes more versatile, promising and important, and have been adopted in most of the current communication standards. Given the actual and future re...
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ISBN:
(纸本)9781479975846
Low density parity check (LDPC) codes are one of the error-correction codes more versatile, promising and important, and have been adopted in most of the current communication standards. Given the actual and future relevance of these codes, we have developed a graphical interface for simulation and performance analysis considering several factors that affect their encoding and decoding. Thus, this interface could be useful in the design process of these codes, and also as a teaching-learning tool on this topic. In addition to the description of the interface and the analysis of simulations, importance of LDPC codes and graphical interfaces is discussed, the set of parameters and criteria considered in the simulations are described and some improvements to the current interface are suggested.
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stocha...
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ISBN:
(纸本)9781479983919
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the bit-flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stocha...
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ISBN:
(纸本)9781479983926
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the bit-flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.
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