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bit-width optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems

IEEE TRANSACTIONS ON COMPUTERS 2015年第11期64卷 3091-3101页

作者： Chung, Jaeyong Kim, Lok-Won Incheon Natl Univ Dept Elect Engn Inchon 406722 South Korea Cisco Syst Inc San Jose CA 95134 USA

This paper presents a novel approach to fractional bit-width optimization of fixed-point designs. We first propose a divide-and-conquer algorithm that can assign optimal fractional bit-widths to a special class of designs that does not have reconvergent paths starting from an internal signal. General designs are partitioned into designs of that special class and our algorithm is applied to each design. The algorithm recursively breaks down a given design into sub-designs and finds Pareto optimal solutions to each sub-design. Those solutions are merged to form Pareto optimal solutions to a larger design. In addition, two pruning methods based on area and error, respectively, are proposed, speeding up the algorithm. The optimization process is guided by static maximum absolute error analysis, and functional correctness is guaranteed for all possible input stimuli. Our approach is demonstrated in five case studies including polynomial approximation and RGB-to-YCbCr conversion, for which the divide-and-conquer algorithm produces the optimal solutions.

关键词： Word-length assignment bit-width optimization finite world-length effects

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Multi-objective Approach for IIR Filter Design and bit-width optimization

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2023年第8期42卷 4836-4867页

作者： Zelmat, Mohammed Lamini, El-Sedik Tagzout, Samir Belbachir, Hacene Belouchrani, Adel USTHB Fac Math RECITS Lab Algiers Algeria Res Ctr Appl Econ Dev Algiers Algeria EPE Proxylan SPA Algiers Algeria CERIST Res Ctr Sci & Tech Informat Algiers Algeria Ecole Natl Polytech LDCCP lab Algiers Algeria

Digital filter design optimization counts as one of the most challenging problems in circuit development. Furthermore, the bit-width allocation has a crucial impact on the efficiency and accuracy of fixed-point digital filters. The conventional implementation procedure involves studying the bit-width allocation problem after determining the filter coefficients. This sequential procedure leads frequently to an excessive bit-width allocation, hence an extra implementation cost. The main contribution of this paper is to propose a new implementation procedure based on the simultaneous handling of both design issues and the bit-width optimization for the infinite impulse response filter. In this study, the problem is formalized by a multi-objective programming technique using the non-dominated sorting genetic algorithm II. The joint consideration of the two problems offers a better trade-off between design and bit-width allocation. The output of our approach is compared to the results of existing algorithms. Simulation results show that the multi-objective method significantly reduces the implementation cost while ensuring filter stability and an acceptable mean square error (MSE) compared to the existing algorithms.

关键词： Filter design System identification bit-width optimization Precision analysis Non-dominated sorting genetic algorithm II IC design

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An Overflow/Underflow-Free Fixed-Point bit-width optimization Method for OS-ELM Digital Circuit

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2022年第3期E105A卷 437-447页

作者： Tsukada, Mineto Matsutani, Hiroki Keio Univ Grad Sch Sci & Technol Yokohama Kanagawa 2238522 Japan

Currently there has been increasing demand for real-time training on resource-limited IoT devices such as smart sensors, which realizes standalone online adaptation for streaming data without data transfers to remote servers. OS-ELM (Online Sequential Extreme Learning Machine) has been one of promising neural-network-based online algorithms for on-chip learning because it can perform online training at low computational cost and is easy to implement as a digital circuit. Existing OS-ELM digital circuits employ fixed-point data format and the bit-widths are often manually tuned, however, this may cause overflow or underflow which can lead to unexpected behavior of the circuit. For on-chip learning systems, an overflow/underflow-free design has a great impact since online training is continuously performed and the intervals of intermediate variables will dynamically change as time goes by. In this paper, we propose an overflow/underflow-free bit-width optimization method for fixed-point digital circuits of OS-ELM. Experimental results show that our method realizes overflow/underflow-free OS-ELM digital circuits with 1.0x - 1.5x more area cost compared to the baseline simulation method where overflow or underflow can happen.

关键词： OS-ELM bit-width optimization fixed-point design

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BWOLF: bit-width optimization for Statistical Divergence with Logarithmic Functions 31

BWOLF: Bit-Width Optimization for Statistical Divergence wit...

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31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Xu, Qian Sun, Guowei Qu, Gang Univ Maryland Dept ECE College Pk MD 20742 USA

ISBN: (纸本)9781728171470

Approximate computing is a promising technique in improving the energy efficiency for error-resilient applications such as multimedia, signal processing and neural network. A large amount of reported work is on the design of approximate computation units with truncated data under error constraints. However, they mainly focus on simple arithmetic operations, addition and multiplication to be more specific. In this paper, we study how to apply the truncation method to the floating-point logarithmic operation which is getting increasingly popular. We analyze the tradeoff between the precision of computation and the energy it requires and derive a formula on the most energy efficient implementation of the logarithm unit for a given error variance range. Based on this theoretical result, we propose BWOLF (bit-width optimization for Logarithmic Function), which uses a sequential quadratic programming algorithm to determine the way to truncate data (i.e., bit-width optimization) in a program with logarithm and other arithmetic operations such that the energy consumption is minimized under a fixed error budget. We evaluate the efficacy of BWOLF in energy saving on two widely used applications: Kullback-Leibler Divergence and Bayesian Neural Network. The experimental results validate the correctness of our analysis and show significant amount of energy saving over both the full-precision computation and the uniform truncation method. The energy savings range from 27.18 % to 95.92% for different error constraints.

关键词： approximate computing bit-width optimization logarithm neural network

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Modeling of ITU-T G.729 codec with bit-width optimization for intensive computation blocks

Modeling of ITU-T G.729 codec with bit-width optimization fo...

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International Conference on Microelectronics

作者： Amiri, Neda Kazemian Fakhraie, Sied Mehdi Hosein-Zadeh, Gholam-Ali Mousavinejad, Sied Mahmoud Univ Tehran Sch Elect & Comp Engn Tehran 14395515 Iran

ISBN: (纸本)9781424418466

In this work, ITU-T G.729 speech codec is precisely modeled using basic building blocks of SIMULINK such as simple adders and multipliers. Therefore, a golden model of the codec which best suits as a reference for its hardware implementation is developed. In a custom hardware design, the precision of the computations, i.e. the optimum number of the bits of the computational blocks should be calculated. The optimum number of the bits of the computational blocks is the minimum word-width that maintains the quality of the output with minimum chip area. Three blocks are selected to extract their bit-true models. The optimum bit-width of the coefficients and the internal computations are measured. These blocks are the pre-processing block, the open loop pitch estimator, and the fixed codebook search block. The former is important in terms of error propagation to the output and the two others are the blocks that demand the most computational power respectively. As such, these blocks are suitable choices to be hardware implemented in a hardware-software co-design project.

关键词： bit-width optimization ITU-T G.729 SIMULINK modeling speech codec

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Modeling of ITU-T G.729 Codec with bit-width optimization for Intensive Computation Blocks

Modeling of ITU-T G.729 Codec with Bit-width Optimization fo...

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2007 International Conference on Microelectronics (ICM'07)

作者： Neda Kazemian Amiri Sied Mehdi Fakhraie Gholam-Ali Hosein-Zadeh Sied Mahmoud Mousavinejad School of Electrical and Computer Engineering University of Tehran Tehran Iran

关键词： bit-width optimization ITU-T G.729 SIMULINK modeling Speech codec

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Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2010年第3期61卷 279-291页

作者： Zhang, Linsheng Zhang, Yan Zhou, Wenbiao Harbin Inst Technol Shenzhen Grad Sch Dept Elect & Informat Engn Shenzhen 518055 Peoples R China

Digital signal processing algorithms are usually developed in floating-point arithmetic. After that floating-point to fixed-point transformation is performed to implement them on fixed-point devices, for higher speed, smaller area and lower power. During this transformation, range analysis is to find the minimum integer bit-widths for signals to prevent overflow. Existing state-of-the-art analytical methods for range analysis are generally based on Affine Arithmetic, which presents two approximation methods for non-affine operations. The Chebyshev approximation provides the best approximation with prohibitive computation expense. The trivial range estimation, which is very efficient for computation, over-estimates the range four times at the worst case. This paper presents a novel approach to let user decide tradeoff between approximation accuracy and complexity of Affine Arithmetic. Case studies and experiments are carried out to demonstrate its efficiency.

关键词： Floating-point to fixed-point transformation Range analysis bit-width optimization Affine arithmetic Tradeoff

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Design and Implementation of an Error-Margin Aware Approach for Non-Uniform Segmentation of Elementary Functions Using Degree-N Polynomial Approximation

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IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING 2023年第10期18卷 1626-1638页

作者： Tahir, Nasrallah Boudraa, Malika Lamini, El-Sedik Harkat, Yacine Bellal, Rima USTHB Lab Commun Parlee & Traitement Signal LCPTS Fac Elect Engn Box 32 Bab Ezzouar 16111 Algeria DMN Ctr Dev Technol Avancees Algiers 16303 Algeria USTHB RECITS Lab Fac Math Bab Ezzouar 16111 Algeria ENSTP Dept Classes Preparatoires Sci & Technol BP 32 Kouba Algeria

Elementary functions are widely integrated in many embedded applications such as speech recognition and signal processing. This paper deals with the issues related to the hardware implementation of those functions. Indeed, a novel efficient Error-Margin aware Approach for non-uniform Segmentation of Elementary Functions using degree-N Polynomial Approximation (EMASEF-NPA) has been proposed. The bit-width optimization (BWO) process has been used to obtain a better representation of the approximation polynomial coefficients. The principle of content-addressable memory (CAM) and Horner's rules have been used in the physical implementation. Functional verification, logical synthesis, and physical implementation were performed using the FPGA platform. The results obtained using EMASEF-NPA approach show a significant reduction, up to 70%, in the number of segments compared to conventional approaches. The findings of the physical implementation show a considerable decrease in area and delay. (c) 2023 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC.

关键词： elementary function polynomial approximation fixed-point arithmetic non-uniform segmentation bit-width optimization FPGA

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High-speed implementation of fractal image compression in low cost FPGA

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MICROPROCESSORS AND MICROSYSTEMS 2016年第PartB期47卷 429-440页

作者： Saad, A-M. H. Y. Abdullah, M. Z. Univ Sains Malaysia Sch Elect & Elect Engn Engn Campus George Town 14300 Malaysia Univ Sains Malaysia Collaborat Microelect Design Excellence Ctr CEDEC Engn Campus George Town 14300 Malaysia

Fractal image compression (FIC) is a very popular coding technique use in image/video applications due to its simplicity and superior performance. The major drawback with FIC is that it is very time consuming algorithm, especially when a full search is attempted. Hence, it is very challenging to achieve a real-time operation if this algorithm is implemented on general processors. In this paper, a new parallel architecture with bit-width reduction scheme is implemented. The hardware is synthesized on Altera Cyclone II FPGA whose architecture is optimized at circuit level in order to achieve a real-time operation. The performance of the proposed architecture is evaluated in terms of runtime, peak-signal-to-noise-ratio (PSNR) and compression efficiency. On average the speedup of 3 was attainable through a bit-width reduction while the PSNR was maintained at acceptable level. Empirical results demonstrate that this firmware is competitive when compared to other existing hardware with PSNR averaging at 29.9 dB, 5.82% compression efficiency and a runtime equivalent to video speed of 101 frames per second (fps). (C) 2016 Elsevier B.V. All rights reserved.

关键词： Fractal image compression FPGA Embedded design bit-width optimization Parallel architecture

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Precision Analysis for an Optimal Parallel IIR Filter's Implementation

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第8期41卷 4512-4546页

作者： Zelmat, Mohammed Lamini, El-Sedik Tagzout, Samir Belbachir, Hacene Belouchrani, Adel USTHB RECITS Lab Dept Operat Res Fac Math Algiers Algeria Res Ctr Appl Econ Dev Algiers Algeria EPE PROXYLAN SPA Lot 1Route Fouka Kolea Tipaza Algeria CERIST Res Ctr Sci & Tech Informat Algiers Algeria Ecole Natl Polytech LDCCP Lab Dept Elect Engn Algiers Algeria

This paper addresses the precision analysis of filters in the parallel form framework. The precision analysis consists of determining suitable fractional bit-widths to set a tradeoff between resource consumption and computational accuracy. Although the stability of the parallel form is relatively better controlled than the related direct form, its bit-width optimization did not receive much consideration in the literature, despite its significant contribution to the optimization of the filter's physical implementation. To carry out the needed bit-width optimization, we present two heuristics based on the Estimation of Distribution Algorithm, which falls within the category of probabilistic model-building genetic algorithm. The performance of the proposed approach is discussed, and compared to chosen benchmarks, the results show that our hardware implementations reduce the cost of the resulted circuits up to 37%.

关键词： bit-width optimization Estimation of distribution algorithm IIR filter Parallel form Precision analysis

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