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A reconfigurable block Cryptographic processor Based on vliw Architecture

China Communications 2016年第1期13卷 91-99页

作者： LI Wei ZENG Xiaoyang NAN Longmei CHEN Tao DAI Zibin State Key Lab of ASIC and System Fudan University Shanghai 200240 China Institute of Information Science and Technology Zhengzhou 450001 China

An Efficient and flexible implementation of block ciphers is critical to achieve information security *** implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of ***,these methods could not achieve a good tradeoff between high-speed processing and *** this paper,we present a reconfigurable vliw processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block *** for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection *** proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing *** has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 *** power consumption is 420 *** kinds of block and hash ciphers were realized in the *** encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.

关键词： block cipher vliw processor reconfigurable application-specific instruction-set

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