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Histogram ordering model-based fast motion estimation

IET IMAGE PROCESSING 2012年第3期6卷 238-250页

作者： Park, S. -J. Hong, S. -M. Lee, H. Jin, S. Jeong, J. Hanyang Univ Dept Elect & Comp Engn Seoul 133791 South Korea Hanyang Univ Dept Intelligent Robot Seoul 133791 South Korea LG Elect Inc SIC Ctr DTVSoC Dept SAT Gr Seoul South Korea

This study proposes two efficient block matching algorithms for fast motion estimation using a histogram ordering model in order to reduce the computational cost of video coding. Since the representative pixels that consist of edge or texture mainly contribute to the block matching criterion, it is important to analyse the details of the current block. To analyse the characteristics of the block with low complexity, the pixel histogram is used for the observation of the block. Based on this pixel histogram for the current block, an optimal block matching order is determined for the lossless fast matching algorithm. In addition, adaptive partial block matching algorithm for lossy fast motion estimation using histogram-based block matching ordering is also presented to further reduce the complexity of block matching. By capturing the representative pixels, block matching distortion is maximised soon enough during the block matching. For this reason, partial block matching is available instead of full block matching, which is also known as a full search algorithm. Our experimental results show that the proposed algorithm not only reduces the computational complexity of block matching criterion, but also tends to maintain the image quality when compared to the conventional fast matching algorithms.

关键词： search problems image quality fast motion estimation Optimisation techniques partial block matching histogram-based block matching ordering model Image and video coding motion estimation pixel histogram full search algorithm block matching algorithms image matching video coding representative pixels block matching criterion image texture Computational complexity Video signal processing block matching distortion computational complexity optimal block matching order computational cost reduction Combinatorial mathematics block matching complexity

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Half-Way Stop Adaptive Pattern Search Algorithm for Motion Estimation and Dedicated VLSI Architecture

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第3期42卷 1617-1638页

作者： Mukherjee, Rohan Biswas, Baishik Vinod, Indubu Gaana Indian Inst Management Bodh Gaya Dept IT & Analyt Prabandh Vihar Bodh Gaya Gaya 824234 Bihar India Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

Motion estimation (ME) plays a vital role in performance of any video codec as it addresses the temporal redundancies existing within consecutive frames in any video sequence. The computational complexity of the ME unit is major with respect to the other blocks in the video codec. Researchers and practitioners prefer to use block matching algorithm for performing ME as it is efficient and simultaneously easy to implement. Some ME algorithms follow fixed search patterns, while the others are adaptive and tries to explore the correlation existing within neighbouring blocks of a video frame. This paper presents a new motion estimation algorithm named half-way stop adaptive pattern search algorithm (HAPSA) that reduces the computation of ME by lowering search points, using a proposed half-way stop technique and adaptive search pattern that can explore both fast and slow motion content in a video frame. The proposed HAPSA applies dual-threshold technique-one for classifying the block between zero motion and nonzero motion vector block and another for checking the accuracy of the motion vector. This helps in optimizing the clock cycle requirement and hardware utilization during VLSI design. The proposed VLSI system demonstrates architectural innovation that supports multiple dataflow models with high data throughput. The principal driving force behind the hardware architecture is an output stationary dataflow model wherein 16 reference frame pixels are broadcasted to all the processing elements every clock cycle. Working at a frequency of 357 MHz, the proposed architecture can process a 422 full HD (1920 x 1080) frames per second. The overall gate count of the design turns to be 49 K gate equivalent. The appreciable results with respect to some of the recent works can motivate one to include the proposed system in portable consumer video devices.

关键词： Motion estimation block matching algorithms Half-way stop adaptive pattern search (HAPSA) Early termination

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Correlation Based Rood Pattern Search (CBRPS) for Motion Estimation in Video Processing

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JOURNAL OF INTELLIGENT & FUZZY SYSTEMS 2019年第6期36卷 5989-5999页

作者： Choudhury, Hussain Ahmed Sinha, Nidul Saikia, Monjul Natl Inst Technol Dept Comp Sci & Engn Silchar Assam India Natl Inst Technol Dept Elect Engn Silchar Assam India NERIST Dept Comp Sci & Engn Nirjuli Arunachal Prade India

To exploit the temporal and spatial redundancy and to expedite the process of video encoding it is required to find the motion Vector (MV) by a process called Motion Estimation (ME). In this paper, optimal motion estimation algorithms based on correlation that exists between consecutive macro blocks in a frame of a video with stopping criteria are proposed. The different neighborhood macro blocks (MB) form the Locality of Reference (LOR) of the candidate macro blocks in the reference frame and these LOR defines the types of algorithms which are named as Correlation Based Rood Pattern Search (CBRPS) in four variations which effectively reduce the search time, computational complexity without compromising the PSNR values i.e. quality of the compensated image. The results obtained are compared with the results with relevant existing techniques to highlight the superior performance of the proposed algorithms. All the proposed algorithms outperform the existing techniques both in terms of computational complexity and PSNR values. Amongst the four proposed algorithms the fourth type of CBRPS i.e. CBRPS_T4 is found to be the best for linear and transverse motion of objects in the videos in terms of computational complexity.

关键词： block matching algorithms MV ME TSS 4SS

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Implementation of K-multi constraint shortest paths (K-MCSP) for video compression

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MULTIMEDIA TOOLS AND APPLICATIONS 2022年第24期81卷 35379-35410页

作者： Kumar, Rajender Kumar, Krishan Mahajan, Shubham Chakraborty, Chinmay Pandit, Amit Kant Shri Mata Vaishno Devi Univ Sch Elect & Commun Engn Katra J&K India Birla Inst Technol Dept Elect & Commun Engn Mesra Jharkhand India

Motion Estimation (ME) is one of the vital components in video coding standards. Many motion estimation techniques are developed by researchers but out of these, motion estimation using block matching algorithm (BMA) is most broadly used for estimating the motion vectors in most efficient manner. Therefore, an efficient representation of motion vectors (MVs) and its transmission is the most crucial step of video coding standards to achieve better coding efficiency with minimum degradation in video quality. Since motion estimation consumed about 70%-90% of total computational power, hence reducing the redundancy and computational complexity is need of hour and one of most widely used area of research in the last few decades. In this paper, first a review of various block matching algorithms along with their limitations is done and then a modified block matching algorithm using quadtree decomposition is proposed for finding the optimal solution for rate distortion trade-off which is termed as rate distortion optimization (RDO) problem in video coding. Moreover, K-Multiple Constrained Shortest Path (K-MCSP) algorithm which uses non-linear function in place of linear function is used for finding the shortest paths & best feasible path instead of Multiple Constrained Shortest Path (MCSP). It is experimentally tested for the first six frames of three benchmarking test video namely News, Mother Daughter and Foreman. In all the cases, distribution of bits among DVF and DFD are calculated and it is found that they satisfy the given constraints. The experimental testing demonstrate that the proposed technique is able to decrease the computational complexity by 8-20% with minimum variation in PSNR for all K-MCSP paths to compromise between DVF and DFD which is not achievable in fixed block size matching algorithms (FSBMA).

关键词： Motion estimation K-multiple constrained shortest path block matching algorithms Quad-tree

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A low power arithmetic unit driven motion estimation and intra prediction accelerators with adaptive Golomb-Rice entropy encoder for H.264 encoders on FPGA

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2024年第1期119卷 69-83页

作者： Vigneash, L. Azath, H. Nair, Lakshmi R. Subramaniam, Kamalraj Arjun Coll Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India VIT Bhopal Univ Sch Comp Sci & Engn Bhopal India MES Coll Engn & Technol Dept Elect & Commun Engn Kunnukara Kerala India Karpagam Acad Higher Educ Dept Biomed Engn Coimbatore India

In the recent era, the utilization of the H.264 encoder has been increasing due to its outstanding performance in video compression. However, compressing video with reduced power is still a challenging issue faced by H.264 encoders. Thus, the proposed study intends to minimize the power consumption of H.264 encoders on FPGA by optimizing the basic components of H.264, thereby enhancing performance. For this purpose, the elements like Motion Estimation, intra-prediction, transform unit and entropy encoder are optimized through the effective schemes introduced in the proposed work. Initially, the Motion Estimation unit can be alternated by optimizing the fundamental components of block matching algorithms. To design the block matching algorithms, the proposed study introduces low-power arithmetic units like an add-one circuit-based Carry SeLect Adder and Sum of Absolute Difference. With the help of these methods, the block matching algorithms has designed, and the Motion Estimation Unit can be effectively optimized. Then, by adopting a comparator-less reusing method, the intra-prediction unit is optimized. Next, the transform unit is optimized by proposing a Steerable Discrete Cosine Transform and finally, the entropy encoders are optimized by combining Golomb and Rice entropy encoders. The proposed study uses the schemes above to improve the efficiency of H.264 encoders on FPGA. The experimental analysis in the proposed study is done using Xilinx software. The simulation results show that the proposed work obtained higher power, LUTs, delay, PSNR, frequency and MSE than other competing methods.

关键词： H.264 encoder Motion estimation block matching algorithms Carry SeLect Adder Intra-prediction unit Entropy encoders

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An advanced center biased search algorithm for block motion estimation

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2002年第3期E85D卷 580-583页

作者： Nisar, H Choi, TS Kwangju Inst Sci & Technol Kwangju 500712 South Korea

An advanced center biased search algorithm for block motion estimation is proposed in this letter. It adopts an innovative center biased search strategy to get correct motion vector. The computational complexity is reduced by strict application of the unimodal error surface assumption and half stop technique. Experimental results show that proposed algorithm has improved performance as compared to the conventional block matching algorithms.

关键词： motion estimation block matching algorithms unimodal error surface assumption

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Fast search algorithms for video coding using orthogonal logarithmic search algorithm

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2005年第2期51卷 552-559页

作者： Soongsathitanon, S Woo, WL Dlay, SS Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

The paper presents a novel fast search algorithm for block base motion compensation called the Orthogonal Logarithmic Search. The performance of the algorithm is evaluated by using standard 176 x 44 pixels quarter common intermediate format (QCIF) benchmark video sequences and the results are compared to the traditional well-known full search algorithm and the suboptimal three step search which is used in international video coding standards such as ISO MPEG-1/2 and ITU-T H.263. The important metrics of time and Peak Signal to Noise Ratio are used to evaluate the novel algorithm. The results show that the strength of the algorithm lies in its speed of operation as it is much faster than both the full search algorithm and the three step search. It has speed advantages of almost 87% and over 23% over the full search and three step search algorithms respectively. Furthermore, the accuracy of the prediction of Orthogonal Logarithmic Search algorithm is comparable to that of the three step search.

关键词： orthogonal logarithmic search motion estimation block matching algorithms low bit rate video coding

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A fast multi pattern motion estimation algorithm based on the nature of error surfaces

A fast multi pattern motion estimation algorithm based on th...

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Conference on Applications of Digital Image Processing XXXI

作者： Nisar, Humaira Choi, Tae-Sun GIST Sch Informat & Mechatron Kwangju 500712 South Korea

ISBN: (纸本)9780819472939

In this paper we propose an algorithm for reducing the complexity of motion estimation module in standard video compression applications, In several video coding standards, motion estimation becomes the most time consuming sub system such as H.264/AVC. Therefore recently research focuses on the development of novel algorithms to save computations with minimal effects over the video distortion. Since real world video sequences usually exhibit a wide range of motion content, from uniform to random, adaptive algorithms have revealed as the most robust general purpose solutions. In this paper a simple, computationally efficient and robust scheme for multi pattern motion estimation algorithm based on the nature of error surfaces has been proposed. A combination of spatial and temporal predictors has been used for multiple initial search center prediction, determination of magnitude of motion and search pattern selection. The multiple initial predictors help to identify the absolute zero motion blocks and true location of global minimum based oil the characteristic of error surfaces. Hence the final predictive search center selected is closer to the global minimum. This results in smaller number of search steps to reach minimum location and increases the computation speed. Further computational speed up has been obtained by considering half stop technique and threshold for minimum distortion point. The computational complexity of the proposed algorithm is drastically decreased (average speedup similar to 43%) whereas the image quality measured in terms of PSNR (similar to.20 dB loss with respect to Full Search) also shows results close to Full Search algorithm.

关键词： Motion Estimation block matching algorithms Unimodal error surface prediction Local minimum Global Minimum Spatial Correlation Temporal Correlation

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Predictive Root Pattern Search Algorithm for Motion Estimation on Mobile Devices 5

Predictive Root Pattern Search Algorithm for Motion Estimati...

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5th IEEE Global Conference on Consumer Electronics

作者： Wu, Chia-Ming Huang, Jen-Yi Taiwan Mao Chong Construct Co Ltd Kaohsiung Taiwan Natl Pingtung Univ Dept Comp Sci & Informat Engn Pingtung Taiwan

ISBN: (纸本)9781509023332

For mobile devices, motion estimation has been the most time-consuming part of video compression. Many fast motion vector block matching algorithms are proposed to decrease time complexity. In our paper, a new algorithm called Predictive Root Pattern Search (PRPS) is proposed. Experimental results show that the image quality of the proposed method is better than that of other block matching methods, especially on large and fast motion video chips.

关键词： Motion Estimation block matching algorithms Mobile Devices

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Parallelization of the Hierarchical Search in Python for High Performance Embedded Systems 5

Parallelization of the Hierarchical Search in Python for Hig...

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5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Panagiotis, Radoglou Grammatikis Evdoxia, Manganopoulou Minas, Dasygenis Univ Western Macedonia Dept Informat & Telecommun Engn Kozani 50100 Greece

ISBN: (纸本)9781467396806

The number of high performance embedded systems that are used for multimedia applications, like video encoding or decoding, has erupted. A key component in video encoding is the motion estimation, which exhibits high computational complexity and hard to meet deadlines. The most popular technique for motion estimation is block matching. The hierarchical search (HS) is a popular and a very fast block matching algorithm that achieves the best image quality, with a very high computational complexity. This complexity is usually handled using parallelization. Our work differentiates from other authors, because it targets parallelization on embedded systems using the Python framework and specifically the Multiprocessing module. The experimental results on parallelization of the HS algorithm on a high performance multi core embedded systems, illustrate the usefulness of our methodology, with speedup up to 1.4.

关键词： Motion Estimation block matching algorithms Hierarchical Search Python Multimedia Mobile High Performance

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