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A Sink Node Trusted Access Authentication Protocol for Mobile Wireless Sensor Network Using block cipher algorithm Based on IoT

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INTERNATIONAL JOURNAL OF WIRELESS INFORMATION NETWORKS 2020年第2期27卷 234-240页

作者： Wang, Qian Chen, Wenxia Wang, Lei Zhoukou Normal Univ Coll Comp Sci & Technol Zhoukou 466001 Henan Peoples R China Zhoukou Senior Tech Sch Zhoukou 466001 Henan Peoples R China Soochow Univ Ctr Informat Dev & Management Suzhou 215006 Jiangsu Peoples R China

Aiming at the problem that mobile nodes in Wireless Sensor Network (WSN) lack credibility verification, a Sink node trusted access authentication protocol using packet cipher algorithm for mobile WSN is proposed based on the Internet of Things (IoT) environment. Firstly, the mobile Sink node is utilized to authenticate the sensor node and verify the platform's credibility of the mobile node. Secondly, pre-stored pseudonyms and corresponding public and private keys of mobile nodes are utilized to realize the anonymity of mobile nodes, and the security proof is given under CK (Canetti-Krawczyk) model. Finally, the block cipher algorithm is introduced, and the advantages of the two algorithms are fused. The correctness and security of the proposed protocol have been proved by the verification experiments. In addition, compared with other authentication protocols, the proposed protocol has lower communication overhead.

关键词： Internet of Things (IoT) Trusted access authentication protocol Wireless Sensor Network (WSN) Mobile Sink nodes CK security model block cipher algorithm

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Fully Pipelined Hardware Implementation of 128-Bit SEED block cipher algorithm

Fully Pipelined Hardware Implementation of 128-Bit SEED Bloc...

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5th International Workshop on Applied Reconfigurable Computing

作者： Yi, Jaeyoung Park, Karam Park, Joonseok Ro, Won W. Yonsei Univ Sch Elect & Elect Engn Seoul 120749 South Korea Inha Univ Coll Informat Technol Seoul South Korea

ISBN: (纸本)9783642006401

As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. High-speed data encoding for cryptography is required especially when sending a large amount of important data with highspeed transmission. In order to accomplish the procedure more efficiently, previous research focused on implementing existing algorithms using hardware accelerators. In this paper, we discuss and propose the FPGA implementation of the SEED block cipher algorithm, which is a Korean national industrial association standard for secured systems. Our implementation, which is written in Verilog HDL, is synthesized and tested on a Virtex-V XC5LX 110T FPGA device. Our results show that the proposed fully pipelined design achieves high throughput and can support as high as 6.4 Gbps network speed. Compared to a full software implementation on the Intel Core 2 Duo 2.53 GHz processor, our implementation provides 34 times higher performance in terms of encoding/decoding throughput.

关键词： Field Programmable Gate Arrays (FPGA) block cipher algorithm Cryptography SEED

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block cipher and Stream cipher algorithm Performance Comparison in a Personal VPN Gateway

Block Cipher and Stream Cipher Algorithm Performance Compari...

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1st International Seminar on Application for Technology of Information and Communication (ISemantic)

作者： Ismoyo, Dimas Dwiki Wardhani, Rini Wisnu Natl Crypto Inst Engn Fac Bogor Indonesia Natl Crypto Inst Bogor Indonesia

ISBN: (纸本)9781509023264

A virtual private network (VPN) extends a private network across a public network, such as the Internet. The purpose of this research study is to implemented ATHS3 stream cipher and VEA block cipher algorithm as the addition of TLS ciphersuites in an SBC Raspberry Pi Model B+ as a personal VPN gateway. It consists three main processes, namely the initialization process, key generation process, and encryption process to secure data that are sent through the VPN. The personal VPN Gateway will obtain cryptographic algorithms, TLS ciphersuites supply from OpenSSL library, and VEA algorithm implementation ciphersuites as the addition of TLS ciphersuites. Implementation of VEA algorithm source code will be made in both of the OpenSSL library and the cryptographic library. This comparative study will be conducted by implementing not only a stream algorithm, but also block cipher algorithm on the same VPN gateway and analyze its performances in order to get the most efficient algorithm to secure data that are sent through the VPN. Not only data transfer rate, but also memory usage measurement in SBC Raspberry Pi Model B+ as personal VPN gateway. The personal VPN gateway works as a bridge between the user's PC and network to secure its communication to internal resources, so data that is transmitted is prevented from attacks. The result of performances analysis will recommend the most efficient cipher algorithm, data transfer rate and memory usage to be implemented in an SBC Raspberry Pi Model B+ as a personal VPN gateway on OpenVPN.

关键词： virtual private network stream cipher algorithm block cipher algorithm Raspberry Pi

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A UML 2.0 Profile to Model block cipher algorithms

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6th European Conference Modelling Foundations and Applications

作者： Balderas-Contreras, Tomas Rodriguez-Gomez, Gustavo Cumplido, Rene Natl Inst Astrophys Opt & Elect Comp Sci Dept Puebla 72840 Mexico

ISBN: (纸本)9783642135941

Current mobile digital communication systems must implement rigorous operations to guarantee high levels of confidentiality and integrity during transmission of critical information. To achieve higher performance, the security algorithms are usually implemented as dedicated hardware functional units attached to the main processing units of the embedded communication system. To save hardware resources, the designer usually performs a number of manipulations in the cipher algorithm lying at the core of the confidentiality and integrity operations to implement a simplified version of it that is suitable to be efficiently used in an embedded environment. This paper describes an extension to UML 2.0 to model the structure of contemporary block cipher algorithms, with the ultimate goal of synthesizing representations in a hardware description language from these models according to a model-driven development principle. This automated process should alleviate design complexity and increase the productivity of the developer during experimentation with different design alternatives.

关键词： block cipher algorithm UML 2.0 profile

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A Performance Model for Reconfigurable block cipher Array Utilizing Amdahl's Law

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2022年第5期E105D卷 964-972页

作者： Qu, Tongzhou Dai, Zibin Liu, Yanjiang Chen, Lin Xia, Xianzhao Inst Informat Sci & Technol Zhengzhou Peoples R China China Automot Technol & Res Ctr Beijing Peoples R China

The existing research on Amdahl's law is limited to multi/many-core processors, and cannot be applied to the important parallel processing architecture of coarse-grained reconfigurable arrays. This paper studies the relation between the multi-level parallelism of block cipher algorithms and the architectural characteristics of coarse-grain reconfigurable arrays. We introduce the key variables that affect the performance of reconfigurable arrays, such as communication overhead and configuration overhead, into Amdahl's law. On this basis, we propose a performance model for coarse-grain reconfigurable block cipher array (CGRBA) based on the extended Amdahl's law. In addition, this paper establishes the optimal integer nonlinear programming model, which can provide a parameter reference for the architecture design of CGRBA. The experimental results show that: (1) reducing the communication workload ratio and increasing the number of configuration pages reasonably can significantly improve the algorithm performance on CGRBA;(2) the communication workload ratio has a linear effect on the execution time.

关键词： coarse-grained reconfigurable block cipher array block cipher algorithm Amdahl's law parallelism performance

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The design and implementation of a block cipher ASIC

The design and implementation of a block cipher ASIC

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4th International Conference on ASIC

作者： Jiang, AP Sheng, SM Fu, YL Liu, Y Ji, LJ Peking Univ Inst Microelect Beijing 100871 Peoples R China

ISBN: (纸本)0780366778

With the rapid progress of information technology, security becomes one of the key factors in information storage, communication and processing. For the reason of speed and security, the requirement for VLSI chips or modules that support data encryption and decryption increases rapidly. The design and implementation of a data ciphering processor (DCP) chip adopting block cipher algorithm is demonstrated in this paper. The cipher algorithm is qualified for commercial use. The plaintext, ciphertext and key are all 64-bit long. A top-down design flow is used in the implementation. Several methods are employed to enhance the security of the chip. A standard-cell library is also developed in the design. All the design and implementation of this DCP are performed in China. A 0.9um. double-layer-metal CMOS technology is adopted for manufacture. The chip achieves the required result in the first time implementation. The encryption/decryption processing speed reaches 40MBit/s.

关键词： CMOS integrated circuits application specific integrated circuits cryptography VLSI integrated circuit design block cipher algorithm ASIC information technology security VLSI chip data ciphering processor top-down design flow standard-cell library double-layer-metal CMOS technology data encryption data decryption 64 bit 0.9 micron 40 Mbit/s

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A new S-box three-layer optimization method and its application

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NONLINEAR DYNAMICS 2023年第3期111卷 2841-2867页

作者： Su, Yuyue Tong, Xiaojun Zhang, Miao Wang, Zhu Harbin Inst Technol Sch Comp Sci & Technol Weihai 264209 Peoples R China Harbin Inst Technol Sch Informat Sci & Engn Weihai 264209 Peoples R China

As a common nonlinear component in block cipher, S-box plays a role of confusion and determines the security strength of the whole block cipher algorithm. How to generate a high-performance S-box has always been a hot research issue. Based on four new proposed theorems, a new proposed chaotic map and artificial jellyfish optimization algorithm, a three-layer optimization method for generating high-performance S-box is proposed in this paper. In the first layer, a S-box with high nonlinearity satisfying bijection is generated by combining the new chaotic map. In the second layer, the differential uniformity of S-box is optimized without reducing the nonlinearity of S-box. In the third layer, based on the artificial jellyfish optimization algorithm, a multi-objective optimization algorithm with nonlinearity and differential uniformity as constraints is proposed to optimize other criteria of the S-box. Finally, a block cipher algorithm is designed by using high-performance S-box, chaotic map, improved generalized Feistel structure, etc. Many tests are carried out for the algorithm including key sensitivity analysis, key space size analysis, confusion and diffusion test and ciphertext statistical analysis, and good results are obtained.

关键词： S-box Three-layer optimization algorithm Chaotic map block cipher algorithm

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Precise Transformation of Feistel to SP Fuse into LFSR

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China Communications 2009年第4期6卷 168-171页

作者： Luo Lan Qu Zehui Song Chaoming School of Computer Science and Technology University of Electronic Science Technology of China ＆ National Laboratory for Modern Communications Chengdu China

For the published block cipher algorithm, two kinds of round functions have been *** ciphers in network environments are taking more risks than ever before because of their initialization key's distribution in the *** security of block cipher algorithm is affected by linear bias and nonlinear bias which are restricted by confusion layer and diffusion *** article takes an approach on how block cipher's two round structures are initially transformed when they fuse into *** SP structure can be considered two F functions in one Feistel round function which combines both right and left of origin data ***, the round number linear function and nonlinear function of Feistel and SP structure are *** merit of SP structure is that it can fuse in LFSR as a nonlinear filter without memory.

关键词： block cipher algorithm precise transformation merit of SP structure fuse in LFSR

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Efficient Multi-Byte Power Analysis Architecture Focusing on Bitwise Linear Leakage

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2024年第6期23卷 1-25页

作者： Jiang, Zijing Ding, Qun Wang, An Heilongjiang Univ Harbin Heilongjiang Peoples R China Beijing Inst Technol Comp Sci Beijing Peoples R China

As the most commonly used side-channel analysis method, Correlation Power Analysis (CPA) usually uses the divide-and-conquer strategy to guess the single-byte key in the scenario of block cipher parallel implementation. However, this method cannot effectively use the power consumption information, resulting in a large number of power consumption traces. Therefore, genetic algorithm-based CPA is proposed, which can efficiently extract keys by multi-byte power analysis. However, genetic algorithm-based CPA tends to sacrifice computational cost to achieve a high key guessing success rate. To solve the above problems, this article focuses on bitwise linear leakage and proposes a multi-byte power analysis architecture based on the raindrop ripple algorithm. First, we propose to complete the key initialization by multiple linear regression. Second, we propose a novel swarm intelligence algorithm, the raindrop ripple algorithm, tailored for multibyte power analysis based on the principles of "family planning" and "eugenics," which greatly improves the probability of producing individuals with high fitness values. Third, we further enhance the possibility of the correct key being recovered by traversing the candidate key space in specific conditions. To verify the key guessing efficiency of the multi-byte power analysis architecture based on the raindrop ripple algorithm, comparative experiments are conducted on SAKURA-G with three power analysis methods based on genetic algorithms. Experimental results show that our proposal not only has the efficient power information utilization of multi-byte power analysis but also has a convergence speed comparable to or even faster than that of single-byte CPA. Its efficiency of key guessing is improved by 85.64% compared to EfficiencyGa-CPA, and its convergence speed is even faster than that of single-byte CPA at 725 power traces, and 83.87% faster than single-byte CPA at 1000 power traces, which is astonishing as a multi-byte power

关键词： block cipher algorithm Correlation power analysis FPGA Genetic algorithm Swarm intelligence

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A Joint Watermarking/Encryption algorithm for Verifying Medical Image Integrity and authenticity in Both Encrypted and Spatial Domains

A Joint Watermarking/Encryption Algorithm for Verifying Medi...

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33rd Annual International Conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBS)

作者： Bouslimi, D. Coatrieux, G. Roux, Ch. Inst Telecom F-29238 Brest 3 France

ISBN: (纸本)9781424441228

In this paper, we propose a new joint watermarking/encryption algorithm for the purpose of verifying the reliability of medical images in both encrypted and spatial domains. It combines a substitutive watermarking algorithm, the quantization index modulation (QIM), with a block cipher algorithm, the Advanced Encryption Standard (AES), in CBC mode of operation. The proposed solution gives access to the outcomes of the image integrity and of its origins even though the image is stored encrypted. Experimental results achieved on 8 bits encoded Ultrasound images illustrate the overall performances of the proposed scheme. By making use of the AES block cipher in CBC mode, the proposed solution is compliant with or transparent to the DICOM standard.

关键词： Biomedical imaging DICOM standard Encryption Entropy Joints Reliability Watermarking advanced encryption standard biomedical ultrasonics block cipher algorithm cryptography image watermarking joint watermarking-encryption algorithm medical image integrity

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