Within present article characteristics of errors definition are being analyzed within coded words of conventional sum codes (Berger Codes). Unrevealed features of earlier unknown errors detection based on self-multipl...
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ISBN:
(纸本)9781665426053
Within present article characteristics of errors definition are being analyzed within coded words of conventional sum codes (Berger Codes). Unrevealed features of earlier unknown errors detection based on self-multiplicity and forms (unidirectional, symmetrical either asymmetrical), were discovered by us, which may be helpful while synthesis of embedded control schemas, for example, by means of boolean complement method. Here we demonstrated, that while implementation of Berger Codes, certain amount of symmetrical as well as asymmetrical plus unidirectional faults within coded words are not being spotted, which considered as a difference compares to prior defined characteristics of malfunction identification within data vectors of Berger Codes only (regarding our abovementioned case, any symmetrical errors are not the matter of identification, but at the same time, any of unidirectional or asymmetrical mistakes are being found, which is useful while errors definition systems synthesis). The share of not traced errors from the entire quantity per Berger Codes with data vectors dimensions r=4...7 is composed of less than 2%, as for Berger Codes with vectors lengths r=8...15, it is even less than 0.5%. The abovementioned factor has significant influence on probabilistic characteristics of errors detection into coded words of Berger Codes: for instance, within prospect of failure absence in single digit order number p=0.9, chance of error identification in coded words Pm is above the value of 0.99 for total noted lengths of data vectors. Application of conventional codes with summation is well thought-out as effective case for embedded control systems synthesis including via boolean complement method, where, data and check digits of coded words are being evaluated by means of diagnostic object itself.
We consider the problem of designing a built-in control circuit with full self-testability of control equipment based on the method of booleancomplement to constant-weight 1-out-of-n codes. A method is proposed for d...
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We consider the problem of designing a built-in control circuit with full self-testability of control equipment based on the method of booleancomplement to constant-weight 1-out-of-n codes. A method is proposed for determining complementary functions considering the formation of the necessary set of test combinations for a complete check of each element of modulo-2 addition in the structure of the booleancomplement block. Due to the introduction of uncertainties in the selection of values, it is possible to minimize the complexity of control functions, which makes it possible to simplify the control logic block. An algorithm for the synthesis of a built-in self-test control circuit based on the method of booleancomplement to a preselected constant-weight 1-out-of-n code is given.
A new architecture for the synthesis of fault-tolerant digital devices, which is easier to implement as compared to the well-known architecture based on triple modular redundancy (TMR), is proposed. The architecture i...
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A new architecture for the synthesis of fault-tolerant digital devices, which is easier to implement as compared to the well-known architecture based on triple modular redundancy (TMR), is proposed. The architecture is implemented based on the booleancomplement principle, which implies the use of a special control block for evaluating complement functions, rather than by introducing exact copies of an original circuit. In practice, its complexity can be significantly lower than the complexity of the original circuit. This makes it possible to synthesize fault-tolerant devices with simpler designs as compared to TMR-based devices. The proposed architecture consists of three blocks: the original circuit, the signal error detection circuit, and the signal correction circuit. The synthesis of a fault-tolerant digital device is aimed at generating the structure of the signal error detection circuit, which implements the idea of duplication of complements. The advantages and disadvantages of the proposed fault-tolerant architecture are discussed. The results of experiments on some combinational benchmarks, which demonstrate the effectiveness of the proposed approach, are presented.
We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal e...
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We propose new fault-tolerant architectures, which, in contrast to the well-known double and triple modular redundancy architectures, include only one copy of the original circuit. In the new architectures, a signal error detection circuit is used to select the functions to be corrected. The circuit is built on the basis of the boolean complement method with parity check of calculations. A generalized architecture with booleancomplement based signal correction is presented. This architecture permits one to design the simplest fault-tolerant circuits. Algorithms for designing signal error detection circuits, as well as examples of their application, are given.
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