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Hardware Addition Over Finite Fields Based On booth-Karatsuba algorithm

COMPUTER JOURNAL 2024年第8期67卷 2643-2666页

作者： Perez, J. Ayuso University Carlos III of Madrid CT Engineering Group Madrid Spain

Two algorithms, both based around multiplication, one defined by Andrew Donald booth in 1950 and the other defined by Anatoly Alexeevitch Karatsuba in 1960 can be applied to other types of operations. We know from recent results that to perform some algebraic transformations it is more efficient to calculate an inverse effect of a smaller magnitude together with an original action with a higher rank, than the initial operation, reaching the final element with less transitions. In this paper, we present an addition algorithm on $\mathbb {Z}/m\mathbb {Z}$ of big-integer numbers based on these concepts, using an alternative to traditional hardware implementation for binary addition based on FULL-ADDER cells, allowing the reduction of space complexity compared with other techniques, such as carry-lookahead, letting us calculate a modular addition in an optimal order complexity of $\mathcal {O}(n)$ without adding more complexity due to reduction operations.

关键词： modular addition booth algorithm Karatsuba algorithm hardware binary adder finite field operations Galois field arithmetic

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Design of Low Power booth Multiplier with Enhance Pre-logic Mechanism Using Verilog 1

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8th Smart Trends in Computing and Communications (SmartCom)

作者： Parsodia, Apurv Jindal, Poonam Natl Inst Technol Kurukshetra Sch VLSI Design & Embedded Syst Design Thanesar Haryana India Natl Inst Technol Kurukshetra Dept Elect & Commun Engn Thanesar Haryana India

ISBN: (数字)9789819713233

ISBN: (纸本)9789819713226;9789819713233

A booth Radix-4 multiplier is a commonly used digital circuit for performing high-speed multiplication of binary numbers in modern microprocessors. Low power consumption is a critical requirement for modern electronic devices and designing a low power booth Radix-4 multiplier has become an important research area. This paper proposes a low-power booth Radix-4 multiplier with improved design by using pre-logic to generate the enable signal (pre-encoder) that uses a new approach to reduce the power consumption by minimizing the switching activity in the circuit by disabling traditional booth encoder and decoder and thus prevent from reductant working. The proposed multiplier achieves a significant reduction in power consumption compared to existing Radix-4 booth multipliers while maintaining high performance and accuracy. The research shows the improved power performance with respect to existing Radix-4 booth multipliers while maintaining high performance and accuracy. The design is implemented using Verilog HDL and simulated using Xilinx Vivado 2020.2. Simulation results demonstrate that the total power is reduced by 5.082% while dynamic power, static power consumption is reduced by 3.002%, 71.298%, respectively, and whereas a significant reduction of LUT by 17.8082%

关键词： booth algorithm Power multiplier Low power multiplier Partial product Radix-4 booth multiplier

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Circuit Level Realization of Low Latency Radix-4 booth Scheme for Parallel Multipliers

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PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES INDIA SECTION A-PHYSICAL SCIENCES 2022年第2期92卷 293-301页

作者： Rahnamaei, Ali Fatin, Gholamreza Zare Islamic Azad Univ Ardabil Branch Dept Elect Engn Ardebil Iran Univ Mohaghegh Ardabili Dept Elect & Comp Engn Ardebil *** Iran

A novel radix-4 booth encoding scheme has been presented in this paper. By means of the modified truth table, the transistor level delay from inputs to the partial products has been reduced to four transistors. Also, the output waveforms are free of glitch due to the utilization of pass-transistor logic. The calculation of propagation delay for the critical path has been provided to show the superior speed performance of the proposed architecture. Based on the simulation results using HSPICE for Taiwan semiconductor manufacturing company 0.18 mu m standard complementary metal-oxide-semiconductor process and 1.8 V power supply, a speed improvement of 24% is obtained compared to the previous architectures when the proposed scheme along with the best reported works have been redesigned and simulated in the same technology platform.

关键词： Parallel multiplier Radix-4 booth encoding scheme booth algorithm High-speed Pass-transistor logic

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A booth-based Digital Compute-In-Memory Marco for Processing Transformer Model

A Booth-based Digital Compute-In-Memory Marco for Processing...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Feng, Zhongyuan Wang, Bo Zhang, Zhaoyang Guo, An Si, Xin Southeast Univ Sch Microelect Nanjing Peoples R China

ISBN: (纸本)9781665450737

Transformer model has achieved excellent results in many fields, owing of its huge data volume and high precision requirements, the traditional analog compute-in-memory circuit can no longer meet its needs. To solve this dilemma, this paper proposes a digital compute-in-memory circuit based on the improved booth algorithm. The 6T SRAM array stores the multiplicand, and the multiplier is encoded by the booth encoder, and then, local computing cell (LCC) read the corresponding value from the array according to the encoding result. These values are finally sent to the dual- mode shift and add module (DMSA) to obtain the computation results. The proposed circuit achieved energy efficiency of 33.11TOPS/W@INT8 and 8.3 TOPS/W@INT16. And the proposed circuit achieved 1.92+ better energy efficiency compared with previous works.

关键词： Transformer model Computing in Memory booth algorithm 6T SRAM Digital Computation

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A new high speed and low power decoder/encoder for Radix-4 booth multiplier

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2021年第7期49卷 2199-2213页

作者： Ghasemi, Mir Majid Fathi, Amir Mousazadeh, Morteza Khoei, Abdollah Urmia Univ Microelect Res Lab Orumiyeh 57159 Iran

The proposed booth decoder/encoder unit is an ultrahigh-speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 mu m CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate-level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30-200% comparing related works and also improves the delay of the multiplier 4-21%. The power consumption and the area of the structure are 477 mu w and 20 x 18 mu m(2), respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

关键词： booth algorithm delay digital multiplier encoder decoder

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Design of Energy Efficient Posit Multiplier 23

Design of Energy Efficient Posit Multiplier

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Jonnalagadda, Aditya Anirudh Uppugunduru, Anil Kumar Veeramachaneni, Sreehari Ahmed, Syed Ershad BITS Pilani Hyderabad Campus Hyderabad Telangana India BV Raju Inst Technol Narsapur Telangana India Gokaraju Rangaraju Inst Engn & Technol Hyderabad India

ISBN: (纸本)9798400701252

Posit number system is an emerging number system which aims to be a competitor to the existing IEEE floating-point number system. The posit number system aims to overcome certain inherent flaws associated with the floating-point system and improve the performance of VLSI arithmetic circuits. Recent studies indicate that posit number system has the potential to vastly improve the performance of deep neural network hardware. As a result, posit arithmetic has become an important area of research. Among all the arithmetic operations in computer arithmetic, the most frequently used is multiplication. Multiplication is ubiquitously used in applications varying from image processing, signal processing to neural networks and machine learning. Multiplication also has an extremely high cost in terms of power, area and delay and thus extensive research work goes into optimisation of the above parameters. In this brief, two new multiplier designs based on the Modified booth algorithm have been proposed- P1 and P2 with novel control logic circuits to reduce dynamic power dissipation. The proposed work also involves the design of a novel sign extension with lower gate count for the Modified booth algorithm. Results have indicated that the proposed designs P1 and P2 achieve an improvement of 24% and 22% respectively in the PDP over the existing designs.

关键词： Posit Floating point Multiplier booth algorithm

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Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN

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INTEGRATION-THE VLSI JOURNAL 2024年 97卷

作者： Kumar, J. Charles Rajesh Kulkarni, Raghavendra. D. Majid, M. A. Bir Tikendrajit Univ Fac Engn & Technol Dept Elect & Commun Engn Imphal Manipur India JNTU Khader Mem Coll Engn & Technol Dept Elect & Commun Engn Hyderabad Telangana India Effat Univ Coll Engn Dept Elect & Comp Engn Jeddah Saudi Arabia

An energy -efficient architecture of high-performance FIR adaptive filter design using approximate distributed arithmetic (DA), which is integrated with canonic signed digit -based triangular common sub expression elimination (CSDTCSE) and carry -resist adder based booth recorder adder (CRABRA) is proposed for noise removal in sensor nodes. Distributed arithmetic is coupled with two signed 32 -bit, 16 -bit radix -8 booth algorithms and approximate computation under 2 -bit adder to design FIR adaptive filter for decreasing partial products (PP) together with accumulation circuits. The truncation of LSB in the PP is presented to approximate the PP to reduce memory complexity and hardware overhead. An approximation recoding adder decreases the energy usage, area, and critical path. Approximate Wallace trees are applied to the PP accumulation to lessen the latency. The canonic signed digit -based triangular common sub -expressions elimination framework is proposed, which significantly reduces a count of logic operators and logic depth in implementing the FIR filter. The proposed algorithm is activated in Verilog coding and synthesized using Xilinx 14.5 ISE simulation software. The proposed design successfully reduces delay, area, and power by maintaining better accuracy with performance.

关键词： FIR adaptive filter Noise Distributed arithmetic (DA) booth algorithm

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Performance Improvement of Radix-4 booth Multiplier on Negative Partial Products 6

Performance Improvement of Radix-4 Booth Multiplier on Negat...

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6th International Conference on Integrated Circuits and Microsystems (ICICM)

作者： Li, Yang Tang, Xiqin Liu, Wanting Qiao, Shushan Zhou, Yumei Shang, Delong Univ Chinese Acad Sci Nanjing Inst Intelligent Technol IMECAS Nanjing Peoples R China Chinese Acad Sci Nanjing Inst Intelligent Technol IMECAS Inst Microelect Nanjing Peoples R China

ISBN: (纸本)9781665458863

The traditional booth decoding applied in Radix-4 booth multiplier algorithm, introduces a lot of complement operations during processing negative partial products, which increases the design complexity and deteriorates the system performance. To handle this issue, combinations of the classification partial products are analyzed to eliminate the complement conversion in certain situations. Based on this algorithm, an improved 16X16 Radix-4 booth multiplier with a novel two-stage decoding process is proposed. The design is implemented with Synopsys Design Compiler under SMIC CMOS 55nm technology. The synthesis results show that this work has improvement on reducing the power consumption, boosting the working speed, and narrowing the circuit size.

关键词： booth multiplier booth algorithm negative partial product positive partial product low power

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Radix-16 booth multiplier using novel weighted 2-stage booth algorithm

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IEICE ELECTRONICS EXPRESS 2014年第13期11卷 20140407-20140407页

作者： Kim, Hyunpil Moon, Sangook Lee, Yongsurk Yonsei Univ Sch Elect & Elect Engn Seoul 120749 South Korea Mokwon Univ Dept Elect Engn Taejon 302729 South Korea

In this study, we propose a radix-16 booth multiplier using a novel weighted 2-stage booth algorithm. Most conventional multipliers utilize radix-4 booth encoding because a higher radix increases encoder complexity. To resolve this problem, we propose the weighted 2-stage booth algorithm. The synthesis results show that the multiplier using the proposed algorithm achieves better power-delay products than those achieved by conventional booth multipliers. We believe that the proposed booth algorithm can be broadly utilized in general processors as well as digital signal processors, mobile application processors, and various arithmetic units that use booth encoding.

关键词： booth algorithm multiplier weighted 2-stage booth algorithm booth encoding

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A Low Power Radix-4 booth Multiplier With Pre-Encoded Mechanism

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IEEE ACCESS 2020年 8卷 114842-114853页

作者： Chang, Yen-Jen Cheng, Yu-Cheng Liao, Shao-Chi Hsiao, Chun-Huo Natl Chung Hsing Univ Dept Comp Sci & Engn Taichung 402204 Taiwan Winbond Elect Corp Taichung 30274 Hsinchu County Taiwan

The radix-4 booth algorithm is widely used to improve the performance of multiplier because it can reduce the number of partial products by half. However, numerous additional encoders and decoders would cause the power consumption of the booth multiplier to be considerable. In this paper, a new radix-4 booth pre-encoded mechanism is proposed to reduce the power consumption of the booth multiplier. The proposed design can effectively reduce the power of the booth multiplier dissipated in the redundant activities by disabling the booth encoders and decoders from unnecessary working. Particularly, since the control signals are generated early at the pipeline input register before the multiplier, the performance of our design is better than the traditional booth multiplier. Based on the TSMC 40 nm technology, the simulation results show that the proposed pre-encoded mechanism can reduce the dynamic and static power by 45% and 65%, respectively, compared to the traditional 16-bit radix-4 booth multiplier. Compared to the previous designs, the proposed design keeps the feature of race-free and has lower power consumption. Even compared to the approximate design, the proposed design has better power efficiency and can provide the exact products.

关键词： booth algorithm low power multiplier power efficiency partial product radix-4 booth multiplier

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