Process scheduling is an important issue in the design and maintenance of hard real-time (HRT) systems. The primary objective of scheduling is to provide a feasible process allocation and sequencing. In this paper we ...
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Process scheduling is an important issue in the design and maintenance of hard real-time (HRT) systems. The primary objective of scheduling is to provide a feasible process allocation and sequencing. In this paper we present a prerun-time schedulingalgorithm which addresses the problem of process sequencing. The algorithm is designed for multiprocessor applications with preemptable processes having release times, computation times, deadlines, and arbitrary precedence and exclusion constraints. The algorithm uses a branch and bound (B&B) implicit enumeration technique to generate a feasible schedule for each processor. The set of feasible schedules ensures that the timing specifications of the processes are observed, and that all the precedence and exclusion constraints between pairs of processes are satisfied. The algorithm was tested using a model derived from the F-18 Mission Computer (MC) Operational Flight Program (OFP). The feasibility of using the algorithm to derive processor utilization factors and to assess the software growth capability of the system is also demonstrated, again using the model. The high cost that would be incurred to reimplement the OFP precluded the application of the algorithm to the actual software in the F-18.
In Shepard and Gagne [1], a branch-and-bound implicit enumeration algorithm is described whose purpose is to generate a feasible schedule, if any, for each processor on a multiprocessing node running hard real-time pr...
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