Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of verylargescaleintegration circuits and systems is of great significance, especially in view of the technological paradigm sh...
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ISBN:
(纸本)9781479961139
Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of verylargescaleintegration circuits and systems is of great significance, especially in view of the technological paradigm shift in recent years from system-on-board to system-on-chip design. This paper investigates and provides new approach to realizing aliasing-free elementary-tree space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test, the paper introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND and XOR/XNOR logic. The process is illustrated in the paper with details of synthesis of space compressors for the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using fault simulation programs ATALANTA, FSIM and HOPE, exemplifying the relevance of the technique from the standpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, making it thus a logical choice in commercial design environments.
Realizing aliasing-free space compressor for built-in self-testing of verylargescaleintegration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years...
详细信息
ISBN:
(纸本)9781424479351
Realizing aliasing-free space compressor for built-in self-testing of verylargescaleintegration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, utilizing well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility ( conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits ( results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.
The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent yea...
详细信息
The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper discusses approach to realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND, OR/NOR and XOR/XNOR logic, respectively. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.
Realizing aliasing-free space compressor for built-in self-testing of verylargescaleintegration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years...
详细信息
Realizing aliasing-free space compressor for built-in self-testing of verylargescaleintegration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.
Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of verylargescaleintegration circuits and systems is of great significance, especially in view of the technological paradigm sh...
详细信息
ISBN:
(纸本)9781479961153
Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of verylargescaleintegration circuits and systems is of great significance, especially in view of the technological paradigm shift in recent years from system-on-board to system-on-chip design. This paper investigates and provides new approach to realizing aliasing-free elementary-tree space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test, the paper introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND and XOR/XNOR logic. The process is illustrated in the paper with details of synthesis of space compressors for the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using fault simulation programs ATALANTA, FSIM and HOPE, exemplifying the relevance of the technique from the standpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, making it thus a logical choice in commercial design environments.
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