Modern SoCs are developed by integrating several hundreds of IPs like hardware accelerators, I/O interfaces, memories, controllers, third party IPs, etc. It mostly uses several interconnects or cache coherent network ...
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ISBN:
(纸本)9781728150253
Modern SoCs are developed by integrating several hundreds of IPs like hardware accelerators, I/O interfaces, memories, controllers, third party IPs, etc. It mostly uses several interconnects or cache coherent network for integration. Such complicated SoCs are prone to design errors that may affect, not only functionality but also performance. Performance bugs are much more difficult to detect in comparison to functional bugs. Even bug free performance will vary for a given application for a given SoC micro architecture and RTL design parameters. In majority of cases, performance bug detection and localization have been conducted manually and these are very challenging tasks. To localize such performance bugs in micro-architecture of various design components or interconnects using emulator/FPGA based enviornment is very challenging task. In this paper, we are discussing three approaches to deal with such problems. One approach deals with detection of critical data paths of the design by drawing directed graph of data paths. Later, dynamic performance simulations are run on those paths of the design by stressing all relevant design units. The second approach is about localization of performance bug. Third approach is to extract the RTL design parameters of the various components and analyze these parameters with various stakeholders before declaring the logic freeze of the device. On applying these, we found some critical performance bugs in design which were not found with conventional techniques. The proposed methodologies reduced overall performance verification time and improved quality of design.
The ability to perform a top-level simulation of a processor is hindered by simulation performance, which can be much slower than unit-level test benches. Simulation performance is also greatly reduced by the presence...
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ISBN:
(纸本)9781467389242
The ability to perform a top-level simulation of a processor is hindered by simulation performance, which can be much slower than unit-level test benches. Simulation performance is also greatly reduced by the presence of an increasing number of cores in a top-level test bench. In this paper, we present the implementation of the Fake CPU UVC, a bus functional model which emulates a real CPU's behavior at its boundaries and drives stimulus alongside the RTL implementation of the CPU. The UVC allows for a much greater amount random stimulus to be driven to the shared cache concurrently with a real CPU with little loss in simulation performance. The UVC drives guided random or unconstrained random stimulus specified in a UVM sequence with transactions potentially aiming to represent high-level operations (stores, prefetches, etc.) or low-level bus transactions (reads, writebacks, etc).
This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent int...
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ISBN:
(纸本)9781450314268
This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through a coherent interconnection fabric. In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator. However, we found that significant extensions need to be made to the conventional BFM methodology in order to capture various data-race cases in simulation, which eventually happen in modern multi-processor systems. Especially essential were faithful imp lementations of the memory consistency model and cache coherence protocol, as well as timing randomization. We demonstrate how such a co-simulation environment can be constructed from existing tools and software. Lessons from our study can similarly be applied to design and verification of other tightly-coupled systems.
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