This paper describes a solid-state sensor for ultra-high-speed (UHS) imaging. The 'Kirana' sensor was designed and manufactured in a 180 nm cmos technology to achieve full-frame 0.7 Megapixel video capture at ...
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ISBN:
(纸本)9780819494320
This paper describes a solid-state sensor for ultra-high-speed (UHS) imaging. The 'Kirana' sensor was designed and manufactured in a 180 nm cmos technology to achieve full-frame 0.7 Megapixel video capture at speeds at 2 MHz. The 30 mu m pixels contain a pinned photodiode, a set of 180 low-leakage storage cells, a floating-diffusion, and a source follower output structure. Both the individual cells and the way they are arranged in the pixel are novel. The pixel architecture allows correlated double sampling for low noise operation. In the fast mode, the storage cells are operated as a circular buffer, where 180 consecutive frames are stored until receipt of a trigger;up to 5 video-bursts per second can be read out. In the 'slow' mode, the storage cells act like a pipeline;the sensor can be read out like a conventional sensor at a continuous frame rate of 1,180 fps. The sensor architecture is fully scalable in resolution since memory cells are located inside each pixel. The pixel architecture is scalable in memory depth (number of frames) as a trade-off with pixel size, dependent on application. The present implementation of 0.7 Mpixels has an array focal plane which is optimized for standard 35 mm optics, whilst offering a competitive 180-frame recording depth. The sensor described has been manufactured and is currently being characterized. Operation of the sensor in the fast mode at 2 million frames per second has been achieved. Details on the camera/sensor operation are presented together with first experimental results.
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