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A dual-exposure wide dynamic range cmos image sensor with 12 bit column-parallel incremental sigma-delta ADC

MICROELECTRONICS JOURNAL 2016年第0期55卷 189-194页

作者： Liu, Yun-Tao Xing, Dong-Yang Wang, Ying Chen, Jie Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Peoples R China SuperPix Microelect Technol Co Ltd Beijing Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

A wide dynamic range cmos image sensor (CIS) based on the synthesis of long and short exposure signals is proposed. To achieve the high-speed readout, a high speed, 12-bit column-parallel incremental sigma-delta (Sigma Delta) ADC including digital correlated double sampling (CDS) is developed to implement the synthesis of dual-exposure data on chip. Since the use of Sigma Delta ADC, it does not require huge frame memory device to store conversion data, the synthesis of long and short exposure images simply and can be easily implemented on CIS chip, and the power dissipation is reduced. The cmos image sensor has been fabricated with 0.18 mu m 1P4M CIS process. This sensor achieves a dynamic range of 95 dB, and the measured results indicate that the random noise is 7e(rms)(-), the pixel conversion gain is 100 mu V/e(-), full well capacity of the pixel is 25000 e(-), and the power dissipation of one ADC is only 32 mu W. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： cmos image sensor Wide dynamic range Sigma-delta ADC Column-parallel

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An Energy/Illumination-Adaptive cmos image sensor With Reconfigurable Modes of Operations

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2015年第6期50卷 1438-1450页

作者： Choi, Jaehyuk Park, Seokjun Cho, Jihyun Yoon, Euisik Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

We present an energy/illumination-adaptive cmos image sensor for distributed wireless sensor applications. The adaptive feature enables always-on imaging operation with extremely low power consumption for extended lifetime of wireless image sensor nodes and provides optimum images in a wide range of illuminations. For adaptive operation, the sensor employs reconfigurable modes of operation. Most of time, the sensor is in a monitoring mode, which keeps imaging at extremely low power consumption. The sensor turns into a high-sensitivity imaging mode or a wide dynamic range imaging mode when illumination varies and sufficient power supply is available from energy harvesting. The sensor changes its operation back to the monitoring mode in order to save energy in the battery. The sensor operates at 1.36 mu W/frame in the monitoring mode from harvested energy and provides high-sensitive (24 V/lx . sec) and wide dynamic range images (99.2 dB) at 867 mu W in battery operation. The chip achieved power FOM of 15.4 pW/pixel. frame in 0.18 mu m technology.

关键词： cmos image sensor cmos imager low power wide dynamic range wireless sensor network wireless sensor node

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A numerical analysis of a cmos image sensor with a simple fixed-pattern-noise-reduction technology

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2002年第5期49卷 746-753页

作者： Yonemoto, K Sumi, H Waseda Univ Dept Elect Informat & Commun Engn Tokyo 1698555 Japan Sony Corp SNC Imaging Device Co Micro Syst Dept Kanagawa 2430014 Japan

A 1/3-in 640 x 480-pixel cmos image sensor with a simple fixed-pattern noise-reduction technology with a five-transistor pixel circuit and a low input-voltage current-voltage (I-V) converter was previously developed. In this report, we show the effectiveness of a low-input-voltage I-V converter with a current-mirror circuit is improving the amplification factor and the linearity of the pixel circuit. In a five-transistor pixel circuit, the threshold voltage of the X-Y addressing transistor effects the amplitude and the level of the readout pulse. An analysis of the mechanism of the X-Y addressing transistor in this report shows the basic concept behind the selection of the threshold voltage. An L-shaped readout gate for a pinned photodiode is compared with a straight readout gate, and it is proved to be adequate for rapid charge transfer.

关键词： active pixel sensor (APS) cmos image sensor correlated double sampling (CDS) fixed-pattern noise (FPN) image lag I-V converter linearity pinned photodiode

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Novel Single-Slope ADC Design for Full Well Capacity Expansion of cmos image sensor

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IEEE sensorS JOURNAL 2013年第3期13卷 1012-1017页

作者： Yeh, Shang-Fu Hsieh, Chih-Cheng Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

This paper proposes a novel single-slope (SS) ADC design and operation for full well capacity (FWC) expansion of cmos image sensor to increase the dynamic range for small pixel. With the proposed technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared with the general double A/D conversion operation. A 160x140 cmos image sensor chip with the proposed SS ADC is fabricated using 0.18-mu m cmos image sensors technology. This chip achieves a sensitivity of 5.33 V/lx-s and a FWC expansion ratio of 2.18 at 38.5 fps. The measured FWC is 47.45 ke(-) with 118% boost. The ADC resolution is 8 bits and the resulting differential nonlinearity/integral nonlinearity of proposed column-parallel SS ADC is (+0.16, -0.24)/(+ 0.28, -0.52) least significant bit. The column-fixed pattern noise is 0.16%.

关键词： cmos image sensor full well capacity single slope ADC small dimension pixel

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Measuring Intra-Pixel Sensitivity Variations of a cmos image sensor

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IEEE sensorS JOURNAL 2018年第7期18卷 2722-2728页

作者： Mahato, Swaraj Bandhu de Ridder, Joris Meynants, Guy Raskin, Gert van Winckel, Hans Katholieke Univ Leuven Inst Sterrenkunde B-3001 Leuven Belgium Ams Sensors Belgium B-2600 Antwerp Belgium

Some applications in scientific imaging, like space-based high-precision photometry, benefit from a detailed characterization of the sensitivity variation within a pixel. A detailed map of the intra-pixel sensitivity (IPS) allows to increase the photometric accuracy by correcting for the impact of the tiny sub-pixel movements of the image sensor during integration. This paper reports the measurement of the sub-pixel sensitivity variation and the extraction of the IPS map of a front-side illuminated cmos image sensor with a pixel pitch of 6 mu m. Our optical measurement setup focuses a collimated beam onto the imaging surface with a microscope objective. The spot was scanned in a raster over a single pixel to probe the pixel response at each (sub-pixel) scan position. We model the optical setup in ZEMAX to cross-validate the optical spot profile described by an Airy diffraction pattern. In this paper, we introduce a forward modeling technique to derive the variation of the IPS. We model the optical spot scanning system and discretize the cmos pixel response. Fitting this model to the measured data allows us to quantify the spatial sensitivity variation within a single pixel. Finally, we compare our results to those obtained from the more commonly used Wiener deconvolution.

关键词： cmos image sensor detectors sensitivity intra-pixel astronomical instrumentation

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A Time-Resolved cmos image sensor With Draining-Only Modulation Pixels for Fluorescence Lifetime Imaging

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2012年第10期59卷 2715-2722页

作者： Li, Zhuo Kawahito, Shoji Yasutomi, Keita Kagawa, Keiichiro Ukon, Juichiro Hashimoto, Mamoru Niioka, Hirohiko Shizuoka Univ Grad Sch Sci & Technol Hamamatsu Shizuoka 4328011 Japan Shizuoka Univ Elect Res Inst Hamamatsu Shizuoka 4328011 Japan Horiba Ltd Adv Res & Dev Ctr Kyoto 6018510 Japan Osaka Univ Grad Sch Engn Sci Osaka 5608531 Japan

This paper presents a time-resolved cmos image sensor with draining-only modulation (DOM) pixels, for time-domain fluorescence lifetime imaging. In the DOM pixels using a pinned photodiode (PPD) technology, a time-windowed signal charge transfer from a PPD to a pinned storage diode (PSD) is controlled by a draining gate only, without a transfer gate between the two diodes. This structure allows a potential barrierless and trapless charge transfer from the PPD to the PSD. A 256 x 256 pixel time-resolved cmos imager with 7.5 x 7.5 mu m(2) DOM pixels has been implemented using 0.18-mu m cmos image sensor process technology with PPD option. The prototype demonstrates high sensitivity for weak signal of less than one electron per light pulse and accurate measurement of fluorescence decay process with subnanosecond time resolution.

关键词： Barrierless cmos image sensor draining-only modulation (DOM) fluorescence lifetime imaging microscopy (FLIM) linearity low noise time-domain lifetime measurement time resolved

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A 256 x 256 cmos image sensor with differential readout and data converter circuits

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2023年第7期51卷 3066-3077页

作者： Karamzadeh, Khadijeh Teymouri, Masood Dousti, Massoud Torkzadeh, Pooya Islamic Azad Univ Dept Elect & Comp Engn Sci & Res Branch Tehran Iran Urmia Univ Technol Fac Elect Engn Orumiyeh Iran

In this paper, a 256 x 256 cmos image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single-slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 mu W. All the circuits are designed and implemented using 0.18-mu m cmos technology in Virtuoso and simulated by the SPECTRE.

关键词： active pixel sensor cmos image sensor comparator noise suppression circuit single-slope ADC

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A wide-dynamic-range cmos image sensor based on multiple short exposure-time readout with multiple-resolution column-parallel ADC

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IEEE sensorS JOURNAL 2007年第1-2期7卷 151-158页

作者： Sasaki, Masaaki Mase, Mitsuhito Kawahito, Shoji Tadokoro, Yoshiaki Sendai Natl Coll Technol Dept Informat & Commun Engn Sendai Miyagi 9893128 Japan Hamamatsu Photon KK Hamamatsu Shizuoka 4358558 Japan Shizuoka Univ Res Inst Elect Hamamatsu Shizuoka 4328011 Japan Toyohashi Univ Technol Dept Comp & Informat Sci Toyohashi Aichi 4418580 Japan

A wide-dynamic-range cmos image sensor based on synthesis of one long and multiple short exposure-time signals is proposed. A high-speed, high-resolution column-parallel integration type analog-to-digital converter (ADC) with a nonlinear slope is crucial for this purpose. A prototype wide-dynamic-range cmos image sensor that captures one long and three short exposure-time signals has been developed using 0.25-mu m 1-poly 4-metal cmos image sensor technology. The dynamic range of the prototype sensor is expanded by a factor of 121.5, compared with the case of a single long exposure time. The maximum DNL of the ADC is 0.3 least significant,bits (LSB) for the single-resolution mode and 0.7 LSB for the multiresolution mode.

关键词： cmos image sensor multiple-exposure multiresolution analog-to-digital converter (ADC) wide dynamic range

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An 11-bit two-step column-shared ADC based on Flash/SS architecture for cmos image sensor

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MICROELECTRONICS JOURNAL 2024年 154卷

作者： Zhao, Qiang Xu, Jitao Fan, Chunhui Wang, Ziming Hu, Ruitong Li, Xin Li, Zhigang Hao, Licai Peng, Chunyu Lin, Zhiting Wu, Xiulong Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Haitusense Co Ltd Hefei 230601 Peoples R China

Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of cmos image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 x 256 pixel resolution, the simulation results show that the row time of ADC is 5.4 mu s, the column-level average power consumption is 129.5 mu W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.

关键词： cmos image sensor Two-step Time compression Multi-column sharing Differential ramps

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Light guide for pixel crosstalk improvement in deep submicron cmos image sensor

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2004年第1期25卷 22-24页

作者： Hsu, TH Fang, YK Lin, CY Chen, SF Lin, CS Yaung, DN Wuu, SG Chien, HC Tseng, CH Lin, JS Wang, CS Natl Cheng Kung Univ Dept Elect Engn VLSI Technol Lab Inst Microelect Tainan 70101 Taiwan Taiwan Semicond Mfg Co Hsinchu Taiwan

Light guide, a novel dielectric structure consisting of PE-Oxide and FSG-Oxide, has been developed to reduce crosstalk in 0.18-mum cmos image sensor technology. Due to the difference in refraction index (1.46 for PE-Oxide and 1.435 for FSG-Oxide), major part of the incident light can be totally reflected at the interface of PE-Oxide/FSG-Oxide, as the incidence angle is larger than total reflection angle. With this light guide, the pixel sensing capability can be enhanced and to reduce pixel crosstalk. Small pixels with pitch 3.0-mum and 4.0-mum have been characterized and examined. In 3.0-mum pixel, optical crosstalk achieves 30% reduction for incidence angle of light at 10degrees.

关键词： cmos image sensor crosstalk light guide

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