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In-Pixel Aperture cmos image sensor for 2-D and 3-D Imaging

IEEE sensorS JOURNAL 2018年第22期18卷 9163-9168页

作者： Choi, Byoung-Soo Kim, Sang-Hwan Lee, Jimin Seong, Donghyun Shin, Jang-Kyoo Lim, Jinyeon Chang, Seunghyuk Park, Jongho Lee, Sang-Jin Kyung, Chong-Min Kyungpook Natl Univ Sch Elect Engn Daegu 41566 South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea Korea Adv Inst Sci & Technol Ctr Integrated Smart Sensors Daejeon 34141 South Korea

This paper presents a cmos image sensor with the in-pixel aperture technique for single-chip 2-D and 3-D imaging. In conventional image sensors, the aperture is located at the camera lens. However, in the proposed image sensor, the aperture is integrated on the cmos image sensor chip and is formed at a metal layer of the cmos image sensor (CIS) process. A pixel array of the image sensor is composed of the W, R, B, and PA pixels (W pixel with integrated metal aperture) for extracting color and depth information. While the image of the W pixel becomes blurred with increasing distance from a focused object, the image of the PA pixel maintains the sharpness. Therefore, the depth image can be obtained using the depth from the defocus method. The size of the pixel, which is based on a four-transistor active pixel sensor with pinned photodiode, is 2.8 mu m x 2.8 mu m. A prototype of the proposed image sensor was fabricated using the 0.11-mu m CIS process and its performance was evaluated.

关键词： Active pixel sensor cmos image sensor pixel aperture 3D imaging

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A Low-Noise cmos image sensor With Digital Correlated Multiple Sampling

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第1期65卷 84-94页

作者： Chen, Nan Zhong, Shengyou Zou, Mei Zhang, Jiqing Ji, Zhongshun Yao, Libin Kunming Inst Phys Kunming 650223 Yunnan Peoples R China

This paper presents a low noise cmos image sensor using conventional 3T active pixel with Nwell/Psub diode as photo detector. Both fixed pattern noise (FPN) and temporal noise are suppressed by the proposed digital correlated multiple sampling (DCMS) technology. FPN and temporal noise from pixel, buffer circuit, and column-parallel ADC are analyzed in detail, and the total noise with DCMS is derived. General expression of 1/f noise with correlated multiple sampling is given, illustrating impact of delay time in DCMS. Output noise of image sensor, frame rate, power, and area are affected by order and oversampling ratio of sigma-delta ADC, which are discussed for practical design. A prototype cmos image sensor with 800x600 pixel array and second-order incremental sigma-delta ADCs is implemented with the 0.35-mu m standard cmos process. Measurement results of the implemented image sensor show a column FPN of 0.009%, an input referred noise of 3.5 e(rms)(-), and a dynamic range of 84 dB with oversampling ratio of 255. This indicates that image sensor with low noise can be achieved by DCMS without the CIS process and column amplification.

关键词： cmos image sensor sigma-delta ADC low noise FPN digital correlated multiple sampling

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A Compressive Sensing-Based cmos image sensor With Second-Order ΣΔ ADCs

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IEEE sensorS JOURNAL 2018年第6期18卷 2404-2410页

作者： Lee, Hyunkeun Seo, Donghwan Kim, Woo-Tae Lee, Byung-Geun Gwangju Inst Sci & Technol Sch Elect Engn & Comp Sci Gwangju 61005 South Korea

This paper presents a new analog-to-digital conversion scheme for a second-order Sigma Delta incremental analog to digital converter (ADC) that can be employed in a compressive sensing (CS)-based cmos image sensor (CIS) as a column-parallel ADC. The conversion scheme removes image distortion from a reconstructed image by making the ADC output codes represent an average of the ADC inputs. In addition, a new multiplexing scheme implementing a compressive sensing matrix helps to reduce hardware complexity and control compression ratio without hardware modifications. A 160 x 160 pixel CS-based CIS fabricated in 0.11 mu m CIS process successfully demonstrates the proposed schemes.

关键词： cmos image sensor Sigma Delta incremental analog to digital converter A/D conversion scheme compressive sensing image processing

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A Low-Power Compression-Based cmos image sensor With Microshift-Guided SAR ADC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2018年第10期65卷 1350-1354页

作者： Zhong, Xiaopeng Zhang, Bo Bermak, Amine Tsui, Chi-Ying Law, Man-Kay Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Hamad Bin Khalifa Univ Coll Sci & Engn Doha Qatar Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China

This brief presents a low-power compression-based cmos image sensor for wireless vision applications. The sensor implements low-bit-depth imaging with planned sensor distortion (PSD) to effectively compress both data bandwidth and processing power while maintaining high reconstruction image quality. Accordingly, a column-parallel microshift-guided successive-approximation-register (SAR) ADC is proposed to enable 3-bit PSD imaging based on a 3 x 3 pattern. To support normal imaging with low area overhead, the circuit is reconfigurable as an 8-bit SAR/single-slope ADC. The data bandwidth is further compressed by a customized lossless encoder based on predictive coding and run length coding. A 256 x 216 prototype imaging system composed of the compression-based image sensor and the lossless encoder is fabricated in a 0.18-mu m standard cmos process. Measurement results show that the image sensor achieves 3 bit/pixel (bpp) with 34.9-dB reconstruction peak signal-to-noise ratio (PSNR) and 0.91 structural similarity index (SSIM). With 1/4 spatial downsampling and lossless encoding, 0.31 bpp is obtained with 29.2-dB PSNR and 0.83 SSIM. The sensor consumes 14.8 mu W (full resolution) and 4.3 mu W (downsampling) at 15 fps, achieving state-of-the-art FoMs of 17.8 and 5.2 pJ/***, respectively. Including the encoder, the overall system dissipates as low as 1.2 mu J/frame, making it an attractive solution for wireless sensor networks.

关键词： cmos image sensor focal-plane compression planned sensor distortion (PSD) low bit depth microshift SAR ADC wireless sensor networks

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Leakage Current Non-Uniformity and Random Telegraph Signals in cmos image sensor Floating Diffusions Used for In-Pixel Charge Storage

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sensorS 2019年第24期19卷 5550-5550页

作者： Le Roch, Alexandre Goiffon, Vincent Marcelot, Olivier Paillet, Philippe Pace, Federico Belloir, Jean-Marc Magnan, Pierre Virmontois, Cedric Univ Toulouse ISAE SUPAERO F-31055 Toulouse France CEA DAM DIF F-91297 Arpajon France CNES F-31055 Toulouse France

The leakage current non-uniformity, as well as the leakage current random and discrete fluctuations sources, are investigated in pinned photodiode cmos image sensor floating diffusions. Different bias configurations are studied to evaluate the electric field impacts on the FD leakage current. This study points out that high magnitude electric field regions could explain the high floating diffusion leakage current non-uniformity and its fluctuation with time called random telegraph signal. Experimental results are completed with TCAD simulations allowing us to further understand the role of the electric field in the FD leakage current and to locate a high magnitude electric field region in the overlap region between the floating diffusion implantation and the transfer gate spacer.

关键词： cmos image sensor floating diffusion sense node leakage current retention time random telegraph signal electric field enhancement

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Column readout circuit with improved offset mismatch and charge sharing for cmos image sensor

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Journal of Semiconductors 2019年第12期40卷 107-111页

作者： Zhongjie Guo Ningmei Yu Longsheng Wu School of Automation and Information Engineering Xi’an University of TechnologyXi’an 710048China Xi’an Microelectronic Technology Institute Xi’an 710054China

High linearity and low noise column readout chain are two key factors in cmos image ***,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for cmos image sensor is proposed in this *** on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two ***,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating *** proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power cmos *** measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.

关键词： cmos image sensor column readout buffer offset mismatch charge sharing

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A Wide Dynamic Range cmos image sensor with a Charge Splitting Gate and Two Storage Diodes

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sensorS 2019年第13期19卷 2904.-2904.页

作者： Lee, Minho Seo, Min-Woong Kim, Juyeong Yasutomi, Keita Kagawa, Keiichiro Shin, Jang-Kyoo Kawahito, Shoji Shizuoka Univ Grad Sch Sci & Technol Hamamatsu Shizuoka 4328011 Japan Shizuoka Univ Res Inst Elect Hamamatsu Shizuoka 4328011 Japan Kyungpook Natl Univ Daegu 702701 South Korea

In this paper, a wide dynamic range (WDR) cmos image sensor (CIS) with a charge splitting gate (SG) and two storage diodes (SDs) is presented. By using single-gate on/off control with the SG, photocurrent path to the first (SD1) or second storage diodes (SD2) is switched alternatively and periodically during exposure and signal electrons generated in a photodiode (PD) are transferred to and accumulated in the SD1 or SD2. By setting a large ratio of the off-time to on-time of the SG, two different sensitivity signals, which are originated by the same photodiode, are generated and a WDR image signal is obtained. This technique has a distinct advantage on mitigating the problem of motion artifact in WDR imaging with high and low sensitivity signals and flexible dynamic control of the dynamic range. An experimental WDR cmos image sensor with 280 (H) x 406 (V)-pixel array consisting of 14 sub-arrays, each of which have 20 (H) x 406 (V) pixels, was implemented and tested. For the SG on/off-time ratio of 30 and 279, the DR of 93 dB and 104 dB, respectively, was demonstrated. The effect of the proposed WDR imaging operation on the reduced motion artifact was experimentally confirmed.

关键词： cmos image sensor storage diode high- and low-sensitivity charge splitting gate (SG) wide dynamic range (WDR)

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Analysis of Disparity Information for Depth Extraction Using cmos image sensor with Offset Pixel Aperture Technique

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sensorS 2019年第3期19卷 472-472页

作者： Choi, Byoung-Soo Lee, Jimin Kim, Sang-Hwan Chang, Seunghyuk Park, JongHo Lee, Sang-Jin Shin, Jang-Kyoo Kyungpook Natl Univ Sch Elect Engn Daegu 41566 South Korea Korea Adv Inst Sci & Technol Ctr Integrated Smart Sensors Daejeon 34141 South Korea

A complementary metal oxide semiconductor (cmos) image sensor (CIS), using offset pixel aperture (OPA) technique, was designed and fabricated using the 0.11-mu m CIS process. In conventional cameras, an aperture is located on the camera lens. However, in a CIS camera using OPA technique, apertures are integrated as left-offset pixel apertures (LOPAs) and right-offset pixel apertures (ROPAs). A color pattern is built, comprising LOPA, blue, red, green, and ROPA pixels. The disparity information can be acquired from the LOPA and ROPA channels. Both disparity information and two-dimensional (2D) color information can be simultaneously acquired from the LOPA, blue, red, green, and ROPA channels. A geometric model of the OPA technique is constructed to estimate the disparity of the image, and the measurement results are compared with the estimated results. Depth extraction is thus achieved by a single CIS using the OPA technique, which can be easily adapted to commercial CIS cameras.

关键词： cmos image sensor disparity information depth extraction

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Nanosecond-Laser induced crosstalk of cmos image sensor 4

Nanosecond-Laser induced crosstalk of CMOS Image Sensor

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4th Seminar on Novel Optoelectronic Detection Technology and Application

作者： Zhu Rongzhen Wang Yanbin Chen Qianrong Zhou Xuanfeng Ren Guangsen Cui Longfei Li Hua Hao Daoliang Elect Equipment Testing Ctr Luoyang Luoyang 471003 Henan Peoples R China

ISBN: (数字)9781510619487

ISBN: (纸本)9781510619487

For the study of pulsed laser induced dazzling of cmos image sensor (CIS), we utilized 1064nm laser to irradiate CIS and changed the laser energy by adjusting the attenuation. The experiment results indicated that, when changing the laser energy, the cmos sensor presented unsaturated crosstalk, saturated cross and semi-crosstalk respectively. And we acquired the threshold of the crosstalk is 2.55e-3mJ/cm(2). It indicates the mechanism analysis that the circuit crosstalk is primary cause and semi-crosstalk is induced by sequential control of Correlated Double Sampling (CDS) circuit and its progressive-scan mode, as when the laser spot was far from the scan-line, the sensor couldn't respond the laser well.

关键词： Laser Dazzling cmos image sensor Crosstalk Threshold Mechanism Analysis

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Design and Simulation of an Application Specific cmos image sensor

Design and Simulation of an Application Specific CMOS Image ...

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IEEE International Conference on Electronics and Communication Engineering (ICECE)

作者： Mudassir, Syed Cao, Xiaoyang Su, Shaojie Chen, Hong Wang, Zhihua Tsinghua Univ Inst Microelect Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781728113043

This paper presents a design and simulation of the voltage mode cmos image sensor (CIS) for a visual aided system, designed for a pose estimation calculation in the total hip replacement surgeries (THR). Firstly, a new imaging system architecture for the application is proposed in this manuscript then a theoretical analysis is discussed to minimize the factors causing nonlinearity in CIS. Secondly, a simulation for the proposed design is presented to give the performance analysis. The cmos image sensor comprises a pixel array of size 200x200, which is designed in TSMC 0.18um 1-poly 6-metal standard cmos process technology with a pixel size of 15um and a fill factor of 60%. Combinational logic with the vertical and horizontal scanning DFF chains have been designed to produce input global control signals and read the output signals generated by each pixel respectively. The simulation results depict the right output signals for each pixel within the respective row and column with the changing input signal. Finally, a complete layout for the proposed design is presented which measures 3mm x 3mm in dimension.

关键词： cmos image sensor floating diffusion fill factor

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