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Novel cmos image sensor pixel to improve charge transfer speed and efficiency by overlapping gate and temporary storage diffusing node

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Chinese Physics B 2021年第1期30卷 593-599页

作者： Cui Yang Guo-Liang Peng Wei Mao Xue-Feng Zheng Chong Wang Jin-Cheng Zhang Yue Hao School of Physics and Optoelectronic Engineering Xidian UniversityXi’an 710071China Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of MicroelectronicsXidian UniversityXi’an 710071China

A novel cmos image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate(OG)and the temporary storage diffusing(TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node(FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.

关键词： cmos image sensor charge transfer efficiency high-speed charge transfer pinned photodiode

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High Frame Rate VGA cmos image sensor using Three Step Single Slope Column-Parallel ADCs

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2015年第1期15卷 22-28页

作者： Lee, Junan Huang, Qiwei Kim, Kiwoon Kim, Kyunghoon Burm, Jinwook Sogang Univ Dept Elect Engn Seoul 121742 South Korea

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA cmos image sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a 0.13 mu m cmos process.

关键词： SS-ADC multi-step ADC cmos image sensor column-parallel ADC

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A 4-M Pixel High Dynamic Range, Low-Noise cmos image sensor With Low-Power Counting ADC

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2017年第8期64卷 3199-3205页

作者： Ma, Cheng Liu, Yang Li, Yang Zhou, Quan Wang, Xinyang Chang, Yuchun Jilin Univ Coll Elect Sci & Engn State Key Lab Integrated Optoelect Changchun 130012 Jilin Peoples R China Gpixel Inc Changchun 130033 Jilin Peoples R China

In this paper, we present a 4-Mpixel high dynamic range (DR), low dark noise cmos image sensor. The pixel design is based on a 4-T PPD structure, with one dedicated High Dynamic Range transistor added in serial with the reset transistor for changing the conversion factor during readout to enhance the DR. A low-power ramp counting Analog to Digital Convertor array is implemented to suppress the structure noise and decrease the power consumption. Measurement results show that when the sensor is operated at a full speed of 47 fps, DR of 87 dB, and dark noise of less than 2e(-) can be achieved. Also the proposed low-power counting method has a dramatic reduction in the current consumed by the column counters during the ADC operation compared with previous documented methods.

关键词： cmos image sensor high dynamic range (DR) low dark noise low power ramp ADC

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A cmos image sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2016年第12期63卷 2180-2188页

作者： Kim, Changhyeon Bong, Kyeongryeol Choi, Sungpill Lee, Kyuho Jason Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea

A low-latency and low-power stereo matching accelerator is monolithically integrated with a cmos image sensor (CIS) for mobile applications. To reduce the overall latency, focal-plane processing is adopted by using the proposed analog census transform circuit (ACTC), and the image readout is pipelined with the following stereo matching process. In addition, a novel focal-plane rectification pixel array (FRPA) merges the rectification with the image readout without any additional processing latency. For area-efficient pixel design, sparse rectification is proposed, and the image rectification is implemented with only two additional switches in each pixel. A stereo matching digital processor (SMDP) is integrated with the CIS for cost aggregation. We present the full design including the layout with a 65 nm cmos process, and the FRPA, the ACTC, and the SMDP achieve 11.0 ms latency with complete stereo matching stages, which is suitable for a smooth user interface. As a result, the 2-chip stereo matching system dissipates 573.9 mu J/frame and achieves 17% energy reduction compared to a previous stereo matching SoC.

关键词： cmos image sensor rectification stereo vision

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A 1Gpixel 10FPS cmos image sensor using pixel array high-speed readout technology

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INTEGRATION-THE VLSI JOURNAL 2023年 89卷 114-122页

作者： Guo, Zhongjie Cheng, Xinqi Xu, Ruiming Su, Changxu Li, Chen Wang, Bin Guo, Youmei Wang, Yangle Xian Univ Technol Dept Elect Engn 5 Jinhua South Rd Jinhua 710054 Zhejiang Peoples R China

In the very large array cmos image sensor (CIS), the very large parasitic resistors and capacitors on the column bus cause very slow charging and discharging speeds and affect the readout speed seriously. In order to solve the problem, this work proposed a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on 55 nm CIS special process, on the premise of not produce additional bus, by tracking the analog signal settling process in real time, self-acceleration is realized in the terminal of the column bus, then the speed of charging and discharging are improved greatly. In the work, the column bus parasitic parameters of 42,624 ?? 24,000 pixels cmos image sensor with 4 ??m pixel pitch are analyzed in detail and a method for establishing self-acceleration of column bus is proposed. The experimental results show that the charging time is shortened from 4??s to 790 ns, and the discharging time is shortened from 22.43??s to 1.17??s under 38.3 pF parasitic capacitance and 26.5 ka parasitic resistance in the column bus. On the one hand, the frame per second (FPS) of the 1Gpixel cmos image sensor reach 10FPS, on the other hand, the column bus tail current can be reduced to 1.5 ??A, which reducing the power consumption of pixel array, and the sampling interval time of the correlation double sampling (CDS) is compressed, so broadened the frequency of noise suppression. While realizing self-acceleration, the additional power consumption single column is less than 10 ??A.

关键词： cmos image sensor High-speed readout Column parallel Correlation double sampling Gigapixel

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Optical performance simulation and optimization for cmos image sensor pixels

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OPTIK 2013年第23期124卷 6330-6332页

作者： Gao, Tie-Cheng Yao, Su-Ying Huo, Xiao-Lei Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China Tianjin Polytech Univ Sch Elect & Informat Engn Tianjin 300387 Peoples R China Ordnance Engn Coll Dept Informat Engn Shijiazhuang 050003 Peoples R China

Finite-difference time-domain (FDTD) method is used to perform three dimension simulations for the optical performance of 1.75 mu m pitch pixels of cmos image sensor. A three dimension pixel model for cmos image sensor pixels is set up. Micro-lens optimization, dielectric stack height reduction can decrease the optical power loss. A SiN layer with proper thickness can reduce the reflection at the Si-SiO2 interface. A high refractive index lightpipe is proposed to confine the light within the pixel. The simulation results show that the optical efficiency of the optimized 1.75 pm pixel compare to that before optimized is promoted by more than 10% and the cross-talk is reduced by 50%. 2013 Elsevier GmbH. All rights reserved.

关键词： FDTD cmos image sensor Simulation Optical efficiency

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cmos image sensor Based Physical Unclonable Function for Smart Phone Security Applications 14

CMOS Image Sensor Based Physical Unclonable Function for Sma...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Cao, Yuan Zalivaka, Siarhei S. Zhang, Le Chang, Chip-Hong Chen, Shoushun Nanyang Technol Univ Sch Elect & Elect Engn 50 Nanyang Ave Singapore 639798 Singapore

ISBN: (纸本)9781479948338

Recent years have seen the rapid growing market of smart phones. At the same time, pirated, knockoff or refurnished phones have also flooded into the worldwide market and inflicted great loss on the mobile phone industry. Existing anti-counterfeiting, authentification and identification methods, which rely on the verification of the IDs stored in the phone memory, are vulnerable to attack. This paper presents a new cmos image sensor based physical unclonable function (PUF) for smart phone identification and anti-counterfeiting. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate the unique signatures. With the proposed differential readout algorithm for the pixels of the fixed pattern noise, the effects of power supply and temperature variations are suppressed. Simulations on a typical 3-T cmos image sensor in GF 65nm cmos technology show that the proposed PUF can generate robust and reliable challenge-response pairs with an uniqueness of 50.12% and a reliability of 100% at temperature varying from 0 degrees C to 100 degrees C and supply voltage variation of +/- 16.7%.

关键词： Physical Unclonable Function process variation smart phone anti-counterfeiting cmos image sensor

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A study of radiation effects of 9 and 12 MeV protons on Chinese cmos image sensor degradation

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Chinese Physics C 2008年第6期32卷 442-445页

作者：孟祥提黄强马艳秀郑永男范平朱升云 Institute of Nuclear and New Energy Technology Tsinghua University China Institute of Atomic Energy

The 9 and 12 MeV proton irradiations of the Chinese cmos image sensor in the fluence range from 1× 10^9 to 4×10^10 cm^-2 and 1 × 10^9 to 2×10^12 cm^-2 have been carried out respectively. The color pictures and dark output images are captured, and the average brightness of dark output images is calculated. The anti-irradiation fluence thresholds for 9 and 12 MeV protons are about 4×10^l0 and 2×10^12 cm^-2, respectively. These can be explained by the change of the concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of cmos image sensor calculated by the TRIM simulation program.

关键词： semiconductor technology cmos image sensor proton irradiation average brightness TRIM simulation

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A Novel Asynchronous Pixel for an Energy Harvesting cmos image sensor

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2011年第1期19卷 118-129页

作者： Shi, Chao Law, Man Kay Bermak, Amine Hong Kong Univ Sci & Technol Smart Sensory Integrated Syst S2IS Lab Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

This paper proposes a novel energy harvesting technique based on an asynchronous pixel structure and an efficient energy generation scheme, referred to as avalanche energy generation (AEG). The key idea behind using an asynchronous type of pixel is to lower the power consumption by enabling only active pixels to be read-out after which they enter into a power generation mode. In this mode, the on-pixel photodetector itself will be used to harvest the light energy from the environment and make it available to active pixels. A very interesting feature about our proposed approach is that during a frame capture, critical energy is mainly required for starting-up activity. Once a group of pixels have been read-out, the available energy will rise and more array activity will contribute to the generation of more energy, hence creating an avalanche effect. In contrast to other early designs of energy harvesting image sensors, our scheme uses the photodetector itself for power generation. This results in better utilization of the photosensitive area and more importantly an improved energy generation scheme. Detailed power analysis and extensive simulation results are provided in this paper, which validate the proposed concept. Three test structures have been fabricated in AMIS 1-poly, 5-metal cmos 0.35-mu m n-well process. The power generation process and event generation have been successfully verified experimentally.

关键词： Address-event-representation cmos image sensor energy harvesting time-to-first-spike pixel

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A 280-μ V Temporal Noise, 76-dB Dynamic Range cmos image sensor With an In-Pixel Chopping-Based Low-Frequency Noise Reduction Technique

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2023年第3期70卷 1134-1142页

作者： Jainwal, Kapil Sarkar, Mukul Indian Inst Technol IIT Bhilai Dept Elect Engn & Comp Sci Sejbahar 492015 Chhattisgarh India Indian Inst Technol IIT Delhi Dept Elect Engn New Delhi 110016 India

In this article, a low-noise cmos image sensor with enhanced dynamic range (DR), using an in-pixel chopping technique, is presented. The proposed in-pixel chopping reduces the low frequency or 1/f noise of the source follower (SF) in an active pixel sensor (APS), which is a major component of the temporal noise. A conventional 3T active pixel, with an n-well/p-sub photodiode (PD), is modified to implement a chopper inside a pixel using only one additional switch. The minimum-sized nMOS transistor acting as a switch is used without much compromising the fill factor (FF). A prototype sensor, with a 128 x 128 pixel array, is fabricated in an Austria Micro Systems (AMSs) 0.35-mu m cmos OPTO process. The pixel pitch is 10.5 mu m with an FF of 30%. The measured temporal noise is 280 mu Vrms at the chopping frequency (f (ch)) of 8 MHz, which shows a reduction in the noise power by 11 dB when compared to a conventional 3T pixel. The reduced noise floor enhances the DR of the pixel from 65 to 76 dB.

关键词： Chopper amplifier cmos image sensor dynamic range (DR) low-frequency noise random-telegraph-signal (RTS) noise

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