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Design of a cmos image sensor Based on a 10-bit Two-Step Single-Slope ADC

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2014年第2期14卷 246-251页

作者： Hwang, Yeonseong Song, Minkyu Dongguk Univ Dept Semicond Sci Seoul South Korea

In this paper, a high-speed cmos image sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

关键词： Two-step single slope ADC cmos image sensor hybrid correlated double sampling

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Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for cmos image sensor

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sensorS 2022年第16期22卷 932-938页

作者： Kato, Norihito Morishita, Fukashi Okubo, Satoshi Ito, Masao Renesas Elect Corp Kodaira Tokyo 1878588 Japan

The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques of column-ADC for surveillance cameras to improve low-light characteristics. RUSH current compensation reduces transient current consumption fluctuations during AD conversion and utilizing timing shift ADCs decreases the number of simultaneously operating ADCs. These proposed techniques improve low-light characteristics because they reduce the operating noise of the circuit. In order to support small signal measurement, this paper also proposes a high-accuracy evaluation system that can measure both small optical/electrical signals in low-light circumstances. To demonstrate these proposals, test chips were fabricated using a 55 nm CIS process and their optical/electrical characteristics were measured. As a result, low-light linearity as optical characteristics were reduced by 63% and column interference (RUSH current) as an electrical characteristic was also reduced by 50%. As for the high-accuracy evaluation system, we confirmed that the inter-sample variation of column interference was 0.05 LSB. This ADC achieved a figure-of-merit (FoM) of 0.32 e-center dot pJ/step, demonstrating its usefulness for other ADC architectures while using a single-slope-based simple configuration.

关键词： cmos image sensor column-parallel ADC multi-functional fine pattern generator on-chip test

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An 84 pW/Frame Per Pixel Current-Mode cmos image sensor With Energy Harvesting Capability

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IEEE sensorS JOURNAL 2012年第4期12卷 720-726页

作者： Tang, Fang Bermak, Amine Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

In this paper, we present an ultra-low-power current-mode image sensor with energy harvesting capability. By biasing the in-pixel transconductance amplifier in triode region and using a pipelined 9-bit current-mode analog-to-digital converter (ADC), a power consumption as low as 84 pW/frame per pixel is achieved. Besides the ultra-low-power feature, the proposed 6T pixel can also be used as a solar cell by reconfiguring the in-pixel P+/Nwell photodiode, which can generate several micro watt power at Klux illumination levels. As a result, this energy harvesting imager is very suitable for wireless image sensor network applications. The test chip with a 128 96 pixel array resolution is fabricated using a 0.35 mu m cmos technology. The random noise and the fixed pattern noise (FPN) in dark are 0.4% and 1%, respectively. In the energy harvesting mode, 4.85 mu W power can be harvested using the reconfigurable pixel array.

关键词： Active pixel sensor (APS) cmos image sensor current-mode energy harvest low-power

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An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for cmos image sensor

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第8期65卷 2524-2533页

作者： Tang, Fang Wang, Zhongjie Xia, Yingjun Liu, Fan Zhou, Xichuan Hu, Shengdong Lin, Zhi Bermak, Amine Chongqing Univ CPS Lab Coll Commun Engn Chongqing 400044 Peoples R China Chongqing Univ Chongqing Engn Lab High Performance Integrated Ci Coll Commun Engn Chongqing 400044 Peoples R China IC Design Ctr SISC Analog IC Design Dept Chongqing 400060 Peoples R China Hamad Bin Khalifa Univ Coll Sci & Engn Doha Qatar Hong Kong Univ Sci & Technol ECE Dept Hong Kong Peoples R China

This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a Sigma Delta analog-to-digital converter-based cmos image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard cmos process. The total chip area of the digital decimation filter is only 4.5x145 mu m(2) per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 mu W under a typical 50-MHz clock frequency.

关键词： cmos image sensor digital decimation filter logic sharing Sigma Delta ADC column-parallel circuit area-efficient

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Covered Microlens Structure for Quad Color Filter Array of cmos image sensor

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CURRENT OPTICS AND PHOTONICS 2023年第5期7卷 485-495页

作者： Hwang, Jae-Hyeok Kim, Yunkyung Dong A Univ Dept ICT Integrated Safe Ocean Smart Citie Busan 49315 South Korea Dong A Univ Dept Elect Engn Busan 49315 South Korea

The pixel size in high-resolution complementary metal-oxide-semiconductor (cmos) image sensors continues to shrink due to chip size limitations. However, the pixel pitch's miniaturization causes deterioration of optical performance. As one solution, a quad color filter (CF) array with pixel binning has been developed to enhance sensitivity. For high sensitivity, the microlens structure also needs to be optimized as the CF arrays change. In this paper, the covered microlens, which consist of four microlenses covered by one large microlens, are proposed for the quad CF array in the backside illumination pixel structure. To evaluate the optical performance, the suggested microlens structure was simulated from 0.5 mu m to 1.0 mu m pixels at the center and edge of the sensors. Moreover, all pixel structures were compared with and without in-pixel deep trench isolation (DTI), which works to distribute incident light uniformly into each photodiode. The suggested structure was evaluated with an optical simulation using the finite-difference time-domain method for numerical analysis of the optical characteristics. Compared to the conventional microlens, the suggested microlens show 29.1% and 33.9% maximum enhancement of sensitivity at the center and edge of the sensor, respectively. Therefore, the covered microlens demonstrated the highly sensitive image sensor with a quad CF array.

关键词： cmos image sensor Covered microlens FDTD simulation Microlens Quad color filter array

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A 1.92-Megapixel cmos image sensor With Column-Parallel Low-Power and Area-Efficient SA-ADCs

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2012年第6期59卷 1693-1700页

作者： Shin, Min-Seok Kim, Jong-Boo Kim, Min-Kyu Jo, Yun-Rae Kwon, Oh-Kyong Hanyang Univ Dept Elect & Comp Engn Seoul 133791 South Korea

This paper presents a cmos image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is 9 mu\m x 425 mu m. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-mu m cmos process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively.

关键词： cmos image sensor column-parallel readout architecture low-power consumption small-area successive approximation analog-to-digital converter (SA-ADC)

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A Relative Imaging cmos image sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

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IEEE sensorS JOURNAL 2015年第7期15卷 4121-4129页

作者： Katic, Nikola Popovic, Vladan Cojbasic, Radisav Schmid, Alexandre Leblebici, Yusuf Swiss Fed Inst Technol Microelect Syst Lab CH-1015 Lausanne Switzerland

This paper proposes an unconventional image acquisition scheme for machine vision applications, based on detecting ratios of illumination (pixel) intensities. Detecting relative ratios enables capturing the scene features and patterns almost independently from the local scene illumination resulting in potentially extremely high dynamic range. Moreover, detecting signal ratios using a fully differential circuit optimally suits the intrinsic nature of very large scale integrated design. A scalable and compact hardware implementation is proposed as a proof-of-concept toward relative image acquisition. The proposed photo-current-ratio-detecting pixels completely bypass the need of conventional photo-current integration which enables high frame-rate operation of up to 24 000 frames/s. The pulse-width-modulated output of the proposed pixel is captured by compact column-parallel readout circuits based on digital counters. The developed 32 x 32 pixel array prototype cmos image sensor consumes 4 mW of power operating at a nominal 9765 frames/s frame rate, and 6.8 mW of power operating at a maximum 24 000 frames/s. The presented prototype design is fully scalable toward newer cmos fabrication nodes and higher sensor resolution.

关键词： cmos image sensor high frame rate HDR relative acquisition contrast imaging machine vision

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THz near-field intensity distribution imaging in the 0.3 THz band using a highly sensitive polarization cmos image sensor using a 0.35 μm cmos process

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JAPANESE JOURNAL OF APPLIED PHYSICS 2024年第3期63卷 03SP66-03SP66页

作者： Okada, Ryoma Mizuno, Maya Nagaoka, Tomoaki Takehara, Hironari Haruta, Makito Tashiro, Hiroyuki Ohta, Jun Sasagawa, Kiyotaka Nara Inst Sci & Technol Div Mat Sci 8916-5 Takayama Ikoma Nara 6300192 Japan Radio Res Inst Natl Inst Informat & Commun Technol 4-2-1 Nukuikitamachi Koganei Tokyo 1848795 Japan Chitose Inst Sci & Technol Dept Optoelect Syst Engn 758-65 Bibi Chitose Hokkaido 0668655 Japan Kyushu Univ Fac Med Sci 3-1-1 MaidashiHigashi ku Fukuoka 8128582 Japan

In this paper, we propose a low-disturbance and fast terahertz (THz) near-field intensity distribution imaging method. The THz detector is fabricated using an oriented multiwalled carbon nanotube (CNT) thin film and a LiNbO3(LN) crystal to the thin film is attached. The CNT absorbs and converts THz waves into heat, and the birefringence change of the LN crystal owing to the heat is used. The birefringence change was measured with high sensitivity using a dual-polarizer configuration of a uniform polarizer and a polarization cmos image sensor. The fabricated THz detector is a low-disturbance method because it does not use metal, and it can measure the THz distribution in the plane all at once, which is faster than the antenna scanning method. Using the proposed method, we have successfully imaged the THz near-field intensity distribution emitted from an impact avalanche and transit time diode oscillating at 0.278 THz.

关键词： cmos image sensor THz imaging Polarization imaging Carbon nanotube

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A Single Slope ADC With Row-Wise Noise Reduction Technique for cmos image sensor

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第9期67卷 2873-2882页

作者： Nie, Kaiming Zha, Wanbin Shi, Xiaolin Li, Jiawen Xu, Jiangtao Ma, Jianguo Tianjin Univ Sch Microelect Tianjin 300072 Peoples R China Tianjin Univ Tianjin Key Lab Imaging & Sensing Microelect Tech Tianjin 300072 Peoples R China

This paper presents a novel technique for single slope analog to digital converter (SSADC) to suppress the rowwise noise in cmos image sensor. A sample switch is used in the current-steering DAC to reduce the noise introduced by bias circuits, which will deteriorate the characteristic of uniformity in the row direction. The sample switch can fix the voltage which biases the current source in the current-steering DAC when generating a ramp to avoid the ramp fluctuation in the time domain. The digital correlated double sampling is used to reduce the non-uniformity in column-level ADCs. The cmos image sensor prototype is fabricated in 110nm 1P3M process. The 10-bit SSADC achieves DNL of -0.20 / +0.15 LSB and INL of -1.35 / +0.91 LSB at a sampling frequency of 29.2 KHz. It is proved that the row-wise noise is reduced from 764 mu Vrmsto 163 mu Vrmsat a frame rate of 228 fps using the proposed sample switch structure. The prototype photos taken by the sensor show that the row-wise noise is reduced under the low-illumination circumstance effectively.

关键词： SSADC cmos image sensor noise reduction

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An event detection module with a low-power, small-size cmos image sensor with reference scaling

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2019年第2期99卷 359-369页

作者： Park, Cheonwi Kim, Woo-Tae Yeo, In-June Jeon, Moongu Lee, Byung-geun GIST Sch Elect Engn & Comp Sci 123 Cheomdangwagi Ro Gwangju 61005 South Korea

This paper presents a low-power and small-size cmos image sensor (CIS) which can be utilized as a power-efficient event detection system. Since high-resolution images are not required for most event detection purposes, power consumption and chip size of the CIS are optimized only for detection performance. The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel. The CIS chip employing a 10m-pitch 3T active pixel occupies a die area of 0.98mmx0.84mm. The CIS dissipates 181W from 3.0V analog and 1.4V digital supplies at the maximum frame rate of 252 fps.

关键词： cmos image sensor Correlated double sampling Event detection Multiple sampling Reference voltage scaling

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