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Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design

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IET circuits DEVICES & SYSTEMS 2015年第5期9卷 362-369页

作者： Monteiro, Cancio Takahashi, Yasuhiro Sekine, Toshikazu Gifu Univ Grad Sch Engn Gifu Japan Gifu Univ Fac Engn Dept Elect Elect & Comp Engn Gifu 50111 Japan

The previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit is implemented in this paper using a multi-stage positive polarity Reed-Muller representation with a composite field technique. The CSSAL and other conventional dual-rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8-bit S-box in order to compare their resistance against side-channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block;thus, the CSSAL S-box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18-m 1.8-V standard complementary metal-oxide semiconductor technology at an operating frequency band of 1.25 KHz-70 MHz.

关键词： low-power electronics cmos logic circuits cryptography Reed-Muller codes low-power secure S-box circuit charge-sharing symmetric adiabatic logic advanced encryption standard hardware design multistage positive polarity Reed-Muller representation composite field technique transitional power fluctuation peak current side-channel attacks triple power clock supplies inversion block SPICE simulation standard complementary metal-oxide semiconductor technology size 0 18 mum voltage 1 8 V word length 8 bit

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Wire crossing constrained QCA circuit design using bilayer logic decomposition

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ELECTRONICS LETTERS 2015年第21期51卷 1677-1678页

作者： Roohi, A. Thapliyal, H. DeMara, R. F. Univ Cent Florida Dept Elect Engn & Comp Sci Comp Architecture Lab Orlando FL 32816 USA Univ Kentucky Comp Architecture Lab Dept Elect & Comp Engn Lexington KY 40506 USA

Quantum-dot cellular automata (QCA) seek potential benefits over cmos devices such as low-power consumption, small dimensions, and high-speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three-step bilayer logic decomposition (BLD) methodology to design QCA-based logic circuits. The partitioning of QCA computing operations into logic layers realises considerable improvements in complexity, area, and modularity metrics. Moreover, since larger circuits are divided into two increasingly disjoint sub-planes, verification of the functionality of the design becomes compartmentalised. Design capability of the proposed approach is illustrated and analysed by implementing an area-efficient full comparator (FC) based on a novel logic realisation. The resulting 1-bit FC achieves 32% improvement in complexity metrics in comparison with the previous optimal QCA-based FC. The related waveforms used in verification of the BLD-generated FC which are obtained by the QCADesigner simulation tool are discussed as a motivating example of the BLD methodology.

关键词： cmos logic circuits cellular automata comparators (circuits) decomposition integrated circuit interconnections integrated circuit modelling logic design low-power electronics power consumption quantum dots wiring BLD methodology BLD-generated FC cmos devices QCA circuit design QCA computing operations QCA-based logic circuits QCADesigner simulation tool area-efficient full comparator bilayer logic decomposition circuit robustness logic layers modularity metrics optimal QCA-based FC power consumption quantum-dot cellular automata wire crossing complexity

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Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

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IET circuits DEVICES & SYSTEMS 2015年第4期9卷 309-318页

作者： Ho, Weng-Geng Chong, Kwen-Siong Gwee, Bah-Hwee Chang, Joseph Sylvester Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

The authors propose an asynchronous-logic (async) quasi-delay-insensitive (QDI) autonomous signal-validity half-buffer (ASVHB) realisation approach for low power sub-threshold operation (V-DD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine-grained gate-level method, which propagates data through a single-cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static-logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub-threshold operation. They compare their ASVHB realisation approach against the competitive reported weak-conditioned half-buffer (WCHB) and pre-charged half-buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require similar to 2.1 x and similar to 1.9 x more transistors than the ASVHB library cells. With respect to a 3-stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 x and 1.5x more transitions per-cycle than the ASVHB pipeline. They design an async 32-bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm cmos process). Their ASVHB ALU occupies 0.092 mm(2), and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require similar to 1.7 x and similar to 1.4x more transistors, respectively, than their design. At the sub-threshold voltage of V-DD = 0.2 V, the WCHB and PCHB counterparts dissipate similar to 1.7x and similar to 2.6x more energy, respectively, and are, respectively, similar to 0.95x and similar to 0.73x slower throughput.

关键词： voltage 0.2 V asynchronous circuits low-power electronics digital arithmetic 3-stage pipeline realisation sub-threshold asynchronous quasidelay-insensitive arithmetic unit weak-conditioned half-buffer single-cell datapath circuit implementation quasidelay-insensitive autonomous signal-validity half-buffer realisation fine-grained gate-level method buffer circuits autonomous signal-validity half-buffer word length 32 bit low power sub-threshold operation pre-charged half-buffer logic unit QDI protocol static-logic implementation cmos cmos logic circuits

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Digital in-situ biasing technique

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ELECTRONICS LETTERS 2015年第12期51卷 897-898页

作者： Hsu, Chun-Wei Kinget, Peter R. Columbia Univ New York NY 10027 USA

A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (cmos) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced cmos process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm cmos process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.

关键词： cmos logic circuits circuit feedback differential amplifiers logic design cmos process cmos technologies analogue CMFB analogue functions analogue interfaces common-mode voltage differential amplifier digital CMFB digital biasing circuit digital biasing scheme digital common-mode feedback circuit digital in-situ biasing solution digital in-situ biasing technique intradie variations nanoscale complementary metal-oxide semiconductor size 65 nm time-based successive approximation conversion ultra-compact digital logic

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Implementation of NOR logic based on Material Implication on CMOL FPGA Architecture 28

Implementation of NOR Logic based on Material Implication on...

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28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems

作者： Mane, Pravin Talati, Nishil Riswadkar, Ameya Jasani, Bhavan Ramesha, C. K. Dept Elect Elect & Instrumentat Engn BITS Pilani KK Birla Goa Campus Zuarinagar 403726 Goa India

ISBN: (纸本)9781479966585

Memristor based nanocrossbar layer fabricated on cmos layer has shown tremendous potential as high density memory and in reconfigurable logic architectures. Instead of having predesigned Configurable logic Blocks (CLBs) and memory for reconfiguration as in FPGA, they can be instantiated in nanocrossbar memory as the need arises. We have shown in this paper, the novel design of NOR block as basic unit of computation for in-memory calculations to implement on CMOL FPGA architecture. This block implements its function using material implication. The proposed scheme is against the naturally arising boolean logic based NOR block in CMOL FPGA.

关键词： cmos logic circuits field programmable gate arrays logic gates CMOL FPGA architecture cmos layer NOR block NOR logic configurable logic blocks material implication memristor based nanocrossbar layer nanocrossbar memory cmos integrated circuits Computer architecture Field programmable gate arrays logic gates Memristors Resistance Wires Field programmable gate arrays material implication logic gates Memristors cmos logic circuits Computer Architecture cmos integrated circuits Rope ELECTRIC WIRE Formal logic NOR

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A 65nm 3.2GHz 44.2mW Low-V_t Register File With Robust Low-Capacitance Dynamic Local Bitlines 41

A 65nm 3.2GHz 44.2mW Low-V<sub>t</sub> Register File With Ro...

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41st European Solid-State circuits Conference (ESSCIRC)

作者： Sarfraz, Khawar Chan, Mansun Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

ISBN: (纸本)9781467374729

This paper presents the highest measured read access frequency for a multi-ported register file (RF) fabricated in a low-power (LP) 1.2V TSMC 65nm low-V-t cmos process. Active power is reduced with the use of low-capacitance dynamic local bitlines (LBLs). The dc noise robustness of low-V-t dynamic LBLs is enhanced by 94% compared to conventional low-V-t dynamic LBLs with novel gated inverter-based read port architecture. The 2-read, 1-write-ported 32-entry x 32-bit per word RF demonstrates measured 3.2GHz operation at 1.2V by consuming 44.2mW of active power and 197.5 mu W of leakage power. The RF is measured down to 0.4V.

关键词： cmos logic circuits digital storage flip-flops low-power electronics LBL TSMC low-Vt cmos process frequency 3.2 GHz low-capacitance dynamic local bitlines multiported register file power 197.5 muW power 44.2 mW read access frequency size 65 nm voltage 0.4 V Capacitance Frequency measurement logic gates Noise Registers Robustness Transistors digital storage cmos logic circuits frequency measurement low-power electronics Registers flip-flops LAWRENCE BERKELEY LABORATORY logic gates Transistor Device Component capacitance low capacitance Noise register file Robustness active power

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A 20 Gb/s 0.3 pJ/b Single-Ended Die-to-Die Transceiver in 28 nm-SOI cmos

A 20 Gb/s 0.3 pJ/b Single-Ended Die-to-Die Transceiver in 28...

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IEEE Custom Integrated circuits Conference (CICC)

作者： Dehlaghi, Behzad Carusone, Anthony Chan Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781479986828

A low-power transceiver architecture 14 die-to-die applications is presented. The proposed transceiver employs cmos logic-style circuits and a passive equalizer in the transmitter to reduce the power consumption. Single-ended signaling without a shared reference voltage is used to minimize the number of required signal traces and packaging bumps. A transceiver prototype is fabricated in 28 mn STM FD-SOI cmos technology and it operates at 20 Gb/s and 16.4 Gb/s data rates over different channels with 5.9 and 7.1 dB of loss relative to DC (10.7 and 12.9 dB total loss) at the Nyquist frequency while consuming 0.30 and 0.33 pJ/bit excluding clocking circuits, respectively.

关键词： cmos logic circuits elemental semiconductors equalisers integrated circuit packaging low-power electronics silicon silicon-on-insulator transceivers STM FD-SOI cmos logic-style circuit technology Si bit rate 16.4 Gbit/s bit rate 20 Gbit/s clocking circuit loss 10.7 dB loss 12.9 dB loss 5.9 dB loss 7.1 dB low-power transceiver architecture packaging bump passive equalizer power consumption single-ended die-to-die transceiver single-ended signaling size 28 nm transmitter Bandwidth cmos integrated circuits Clocks Multiplexing Receivers Transceivers Transmitters

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Closed-form analysis of DC noise immunity in subthreshold cmos logic circuits

Closed-form analysis of DC noise immunity in subthreshold CM...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Massimo Alioto Department of Information Engineering University of Sienna Italy Berkeley Wireless Research Center University of California Berkeley USA

In this paper, subthreshold static cmos logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm cmos technology.

关键词： Circuit noise cmos logic circuits MOSFETs Threshold voltage MOS devices Semiconductor device modeling cmos technology Process design Noise robustness Immune system

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Measuring SET Pulsewidths in logic Gates using Digital Infrastructure

Measuring SET Pulsewidths in Logic Gates using Digital Infra...

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15th International Symposium on Quality Electronic Design (ISQED)

作者： Veeravalli, Varadan Savulimedu Steininger, Andreas Schmid, Ulrich Vienna Univ Technol Dept Comp Engn Vienna Austria

ISBN: (纸本)9781479939466

We present a purely digital infrastructure for measuring SET pulsewidths in logic gates. Such a facility is crucial for experimentally studying radiation sensitivity and SET propagation of a circuit. Our digital-only implementation facilitates measurement within a standard-cell cmos chip, without the need of any analog or customized circuitry on-chip. Besides high resolution and area efficiency, a fundamental requirement guiding the development of our solution was radiation tolerance, as it shall be employed on a test chip that is fully exposed to radiation in an experimental study. We validate our architecture, for various primary radiation target circuits, by analog simulation, injecting SETs of varying strength using the standard double-exponential current model.

关键词： cmos logic circuits logic gates radiation hardening (electronics) SET propagation SET pulsewidth measurement analog simulation digital infrastructure double-exponential current model logic gates radiation sensitivity radiation target circuits radiation tolerance standard-cell cmos chip Inverters logic gates Pulse measurements Radiation detectors Ring oscillators Switches

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Improvement of noise tolerance analysis in deep-submicron low voltage dynamic cmos logic circuits

Improvement of noise tolerance analysis in deep-submicron lo...

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International Conference on Electronic Devices, Systems and Applications (ICEDSA)

作者： Manisha Pattanaik Fazal Rahim Khan Muddala V. D. L. Varaprasad ABV Indian Institute of Information Technology and Management Gwalior Madhya Pradesh India

ISBN: (纸本)9781424466290;9781424466320

Dynamic cmos logic circuits are widely employed for improved performance of VLSI chips. However, dynamic cmos circuits are less resistant to noise than static cmos circuits. We have given an overview of previous techniques employed for improving noise tolerance and then compared these techniques with the proposed techniques. The average noise threshold energy (ANTE) and the Energy normalized ANTE metrics have been used to quantify the noise immunity and power consumption improvement. A 2 input AND gate has been designed using the proposed techniques. Then a comparison analysis has been carried out by realizing and simulating the logic circuits in 180nm and 90nm technology at supply voltages of 1.8V and IV respectively. At 180nm technology the ANTE and Energy normalized ANTE are improved by 7.14X and 4X while for 90nm technology the ANTE and Energy normalized ANTE are improved by 1.88X and 1.65X over the conventional domino logic circuit for the proposed technique.

关键词： Circuit noise Tolerance analysis Low voltage cmos logic circuits Clocks logic circuits Very large scale integration Delay Energy consumption Analytical models

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