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15th International Symposium on Quality Electronic Design (ISQED)

作者： Hsueh, Sung S. -Y. Huang, Ryan H. -M. Wen, Charles H. -P. Natl Chiao Tung Univ Dept Elect & Comp Engn Hsinchu 300 Taiwan

ISBN: (纸本)9781479939466

Soft error has become one of the most critical reliability issues for nano-scaled cmos designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its system-level effect has not yet been investigated with statistical soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS'85) using a 45nm cmos technology is f rst observed under different temperatures for SER. As a result, a SER increase (2.16X more) is found on c17 as the ambient temperature elevates from 25 degrees C to 125 degrees C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and much higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework that integrates statistical cell modeling to consider the ambient temperature (T-a) and the temperature variation (T-v), simultaneously. Experimental result shows that our SSER analysis framework is highly effcient (with multiple-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.

关键词： cmos logic circuits combinational circuits integrated circuit design integrated circuit modelling integrated circuit reliability radiation hardening (electronics) statistical analysis cmos technology Monte-Carlo SPICE simulation SER increase TASSER analysis framework ambient temperature combinational circuits design complexity nanoscaled cmos design operational temperatures particle strike pulse width reliability issue size 45 nm statistical SER analysis statistical cell modeling system-level effect temperature 25 degC to 125 degC temperature variation temperature-aware SSER analysis framework temperature-aware statistical soft-error-rate analysis framework Circuit faults Integrated circuit modeling Load modeling logic gates TV Temperature distribution Transient analysis

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Digital Pulse-Width Pulse-Position Modulator in 28 nm cmos for Carrier Frequencies up to 1 GHz

Digital Pulse-Width Pulse-Position Modulator in 28 nm CMOS f...

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IEEE Radio Frequency Integrated circuits Symposium (RFIC)

作者： Digel, Johannes Groezing, Markus Schmidt, Martin Berroth, Manfred Haslach, Christoph Univ Stuttgart Inst Elect & Opt Commun Engn Stuttgart Germany Alcatel Lucent Deutschland GmbH Bell Labs D-70435 Stuttgart Germany

ISBN: (纸本)9781479976423

A fully digital pulse-width pulse-position modulator (D-PWPM) is proposed that is capable of providing pulse sequences for a switching-mode power amplifier. The pulse sequences are generated according to 6-bit digital input words defining the positions of the rising and falling edges without the need for tunable analog delay cells. All possible edge positions are derived by division and phase interpolation of a digital input clock signal that is a multiple of the carrier frequency. cmos selectors provide two signals which carry the actual rising and falling edge positions to special symmetric cmos NOR and NAND gates. They finally generate the modulated pulse sequence. The D-PWPM is fabricated in a 28 nm low-power cmos technology and the circuit core dissipates 53 mW from a 1 V supply. Sinusoidal double-sideband suppressed-carrier modulation of a 1 GHz carrier demonstrates the capability of the D-PWPM to operate as an RF bandpass mode DAC. With a carrier frequency of 983.04 MHz, an SFDR of 45.6 dB is achieved for a low-frequency modulation and 33.4 dB near Nyquist frequency. Data transmission at 491.52 MBit/s is demonstrated with a 16-QAM.

关键词： cmos analogue integrated circuits cmos logic circuits UHF power amplifiers logic gates low-power electronics modulators pulse position modulation pulse width modulation 16-QAM cmos selectors D-PWPM NAND gates Nyquist frequency RF bandpass mode DAC carrier frequency data transmission digital input clock signal digital pulse-width pulse-position modulator frequency 1 GHz frequency 983.04 MHz low-frequency modulation low-power cmos technology phase interpolation power 53 mW pulse sequences sinusoidal double-sideband suppressed-carrier modulation size 28 nm switching-mode power amplifier symmetric cmos NOR gates voltage 1 V word length 6 bit Clocks Layout logic gates Modulation Power amplifiers Pulse measurements Switches

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A 275 Gbps AES Encryption Accelerator Using ROM-based S-Boxes in 65nm

A 275 Gbps AES Encryption Accelerator Using ROM-based S-Boxe...

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IEEE Custom Integrated circuits Conference (CICC)

作者： Erbagci, Burak Akkaya, Nail Etkin Can Teegarden, Craig Mai, Ken Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)9781479986828

The implementation he SubBytes for S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256x8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk cmos which operates at 2.2GHz and consumes 523mW at 1.0V, 27 degrees C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.

关键词： cmos logic circuits cryptography logic gates pipeline arithmetic read-only storage AES algorithm AES encryption accelerator cmos CTR ROM based S-boxes SubBytes step advanced encryption standard bit rate 275 Gbit/s counter-mode operation frequency 2.2 GHz logic gate S-Box pipelined AES-128 encryption accelerator power 523 mW size 65 nm temperature 27 degC voltage 1.0 V Clocks Decoding Encryption logic gates Read only memory Throughput

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A 110-250V 2MHz isolated DC-DC converter with integrated high-speed synchronous three-level gate drive

A 110-250V 2MHz isolated DC-DC converter with integrated hig...

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IEEE Energy Conversion Congress and Exposition

作者： Lin Cong Hoi Lee Dept. of Electr. Eng. Univ. of Texas at Dallas Richardson Dallas TX USA

ISBN: (纸本)9781467371520

This paper presents techniques for high-voltage isolated converters to achieve high power efficiency at high switching frequencies. To minimize the converter switching loss, an isolated quasi-square-wave zero-voltage switching three-level half-bridge architecture is adopted. An integrated synchronous three-level gate driver is proposed to ensure reliability of all eGaN power FETs and provide fast propagation delays for high-frequency converter operation. Thanks to the auto-reconfigurability of the proposed V_(SW)-based dead-time controller in the gate driver, ZVS of all power FETs with minimal body diode conduction loss can be achieved in a wide input range (110V-250V) to guarantee the reliability of the proposed converter. Implemented in a 0.7μm 700V cmos-LDMOS process, the proposed gate driver achieves ≤ 18ns propagation delays and enables a 250V 45W isolated three-level converter to achieve the peak power efficiencies of 94.2% and 89.1% at 1MHz and 2MHz, respectively.

关键词： cmos logic circuits DC-DC power convertors III-V semiconductors bridge circuits device drivers elemental semiconductors integrated circuit reliability logic gates power field effect transistors power semiconductor diodes switching convertors VSW-based dead-time controller converter switching loss minimization eGaN power FET reliability frequency 2 MHz high power efficiency high switching frequencies high-voltage isolated converters integrated high-speed synchronous three-level gate driver isolated DC-DC converter isolated quasi-square-wave three-level half-bridge architecture isolated zero-voltage switching three-level half-bridge architecture minimal body diode conduction loss peak power efficiencies power 45 W propagation delays voltage 110 V to 250 V voltage 700 V Capacitors Field effect transistors IP networks logic gates Switches Windings Zero voltage switching

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On-chip readout circuit for nanomagnetic logic

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IET circuits DEVICES & SYSTEMS 2014年第1期8卷 65-72页

作者： Liu, Baojun Cai, Li Zhu, Jing Kang, Qiang Zhang, Mingliang Chen, Xiangye Air Force Engn Univ Coll Sci Xian 710051 Shannxi Peoples R China First Aviat Univ Air Force Dept Aviat Ammunit Engn Xinyang 464000 Henan Peoples R China Northwest A&F Univ Coll Food Sci & Engn Yangling 712100 Shannxi Peoples R China Air Force Engn Univ Dept Sci Res Xian 710051 Shannxi Peoples R China

An interface for reading the output of nanomagnetic logic (NML) is indispensable in order for NML to interact with existing cmos ICs. Two alternative designs readout interface circuit (RIC1 and RIC2) for NML RIC are proposed based on dual barriers magnetic tunnel junction (DBs-MTJ), which is composed of two fixed layers (with anti-parallel magnetisation state) and a common free layer. RIC1 utilises the same layer order of DB-MTJ to form an up-down structure, whereas RIC2 exploits the reversed layer order of DB-MTJ to form a left-right structure. They utilise the three-terminal approach to realise the self-reference readout scheme. The magnetisation state of the free layers in RIC1 and RIC2 are controlled by the fringing field from NML and biased by the designed on-chip clock field. The sensing circuits in RIC1 and RIC2 utilise dynamic current mode and pre-charge sense amplifier, respectively. The simulation results indicate that RIC1 and RIC2 can achieve comparable magnetoresistance values, and also realise the logical readout scheme by itself. The switching time in RIC1 is less than that in RIC2, whereas time delay for data transportation in RIC1 is more than that in RIC2. RIC2 is more amenable than RIC1 to the current fabrication process technology.

关键词： cmos logic circuits delays magnetisation magnetoresistance preamplifiers readout electronics nanomagnetics on-chip readout circuit nanomagnetic logic NML readout interface circuit NML RIC dual barrier magnetic tunnel junction antiparallel magnetisation state DB-MTJ up-down structure RIC2 left-right structure three-terminal approach self-reference readout scheme magnetisation state fringing fleld on-chip clock fleld dynamic current mode precharge sense amplifler magnetoresistance value logical readout scheme data transportation fabrication process technology time delay

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A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor

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IET circuits DEVICES & SYSTEMS 2014年第6期8卷 427-434页

作者： Zhu, Zhangming Qiu, Zheng Shen, Yi Yang, Yintang Xidian Univ Sch Microelect Xian 710071 Peoples R China

A design of a 10-bit 27.8 kS/s 0.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage design. To facilitate ultra-low voltage operation, a bulk-driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to relieve non-linearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal-to-noise distortion ratio and 8.4-bit effective number of bits resulting in a figure-of-merit of 2.67 fJ/conversion-step.

关键词： double-boosted sample switch flip-flops complementary metal oxide semiconductor segmented-capacitor array structure boosting technique power 25.2 nW digital-to-analogue converter driving switch successive approximation register analogue-to-digital converter bulk-driven-based fully-dynamic comparator latched dynamic logic cell ultralow-voltage design nanowatt range power consumption ultralow-voltage operation size 65 nm word length 10 bit leakage current reduction sampling linearity comparators (circuits) signal-to-noise distortion ratio decision error elimination ultralow-power SAR ADC design figure-of-merit analogue-digital conversion voltage 0.35 V cmos logic circuits

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Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

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IET circuits DEVICES & SYSTEMS 2014年第2期8卷 73-81页

作者： Yuwono, Sigit Han, Seok-Kyun Yoon, Giwan Cho, Han-Jin Lee, Sang-Gug Korea Adv Inst Sci & Technol Dept Informat & Commun Engn Taejon 305701 South Korea Korea Adv Inst Sci & Technol Dept Elect Engn Taejon 305701 South Korea ETRI SW SoC Convergence Res Lab Taejon South Korea

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit Delta sigma frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm cmos technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 mu s of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

关键词： phase-and-frequency detector ADFLL frequency 500 MHz phase detectors distributed pulsewidth word length 1 bit under-sampled Î”Î£ frequency-to-digital converters size 90 nm field-programmable gate array delta-sigma modulation on-chip reference clock generator cmos technology frequency locked loops comparators (circuits) field programmable gate arrays reference circuits power 2.64 mW low-complexity all-digital frequency locked loop voltage 1.2 V frequency comparator cmos logic circuits

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Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

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IET circuits DEVICES & SYSTEMS 2014年第6期8卷 526-531页

作者： Arunachalam, V. Raj, Alex Noel Joseph Vellore Inst Technol Univ Sch Elect Engn Vellore 632014 Tamil Nadu India

In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley-Tukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed 'pass-logic'. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and 'pass-logics'. The performance improvements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 mu m 1P6M cmos process.

关键词： OFDM modulation hardware power FFT processing wireless LAN binary phase shift keying twiddle multipliers size 0.18 mum 128-point FFT implementation trivial multiplications fast Fourier transforms power 6.45 mW 64-point FFT quadrature phase shift keying digital modulation pass-logic Cooley-Tukey-based DIF FFT architecture IFFT processing unit fast Fourier transform complementary metal oxide semiconductor process very large scale integration implementation frequency 20 MHz hardware area IEEE 802.11a wireless local area network application orthogonal frequency division multiplexing-based digital transmitter performance improvements FFT-IFFT implementation Cooley-Tukey-based decimation-in-frequency FFT architecture field programmable gate arrays FPGA voltage 1.8 V VLSI quadrature phase shift keying cmos logic circuits

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Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits

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IET COMPUTERS AND DIGITAL TECHNIQUES 2014年第2期8卷 83-89页

作者： Valenti, Lorenzo Dalpasso, Marcello Favalli, Michele Univ Ferrara ENDIF I-44122 Ferrara Italy Univ Padua DEI I-35131 Padua Italy

This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.

关键词： automatic test pattern generation cmos logic circuits combinational circuits computability fault simulation integrated circuit testing logic testing combinational benchmarks SAT-based test generation procedure single simulation step faulty behaviours faulty cell throughout bit-level parallelism symbolic fault simulation algorithm multioutput combinational logic cells nanocomplementary metal oxide semiconductor integrated circuits

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Distributed range-free localisation algorithm for wireless sensor networks

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ELECTRONICS LETTERS 2014年第12期50卷 894-+页

作者： Chen, Liangyin Li, Miao Liu, Kai Liu, Zhenlei Zhang, Jingyu Peng, Tong Liu, Yan Xu, Yongjun Luo, Qian He, Tian Sichuan Univ Sch Comp Sci Chengdu 610064 Peoples R China Sichuan Univ Sch Elect Engn & Informat Chengdu 610064 Peoples R China Peking Univ Sch Software & Microelect Beijing 100871 Peoples R China Chinese Acad Sci Inst Comp Technol Wireless Sensor Network Lab Beijing Peoples R China Second Res Inst Gen Adm Civil Aviat China Informat Technol Branch Chengdu Peoples R China Univ Minnesota Twin City Dept Comp Sci & Engn Minneapolis MN USA

A novel distributed range-free localisation algorithm to accurately locate regular nodes in wireless sensor networks is presented. Existing methods reduce the possible area where a regular node would be located by using anchors (i.e. nodes with known locations) only. These methods are effective only when anchor density is high. In contrast, the work presented here reduces the possible area of a regular node iteratively, using both anchor node locations and the possible areas of its neighbouring and non-neighbouring 'regular' nodes from early iteration. This allows a significant improvement in the localisation accuracy. Simulations verify the advantage of the proposed algorithm and show that the localisation error can be controlled within 15% with off-the-shelf devices.

关键词： ALGORITHMS RESEARCH WIRELESS communication systems LOCALIZATION (Mathematics) WIRELESS sensor networks cmos logic circuits

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