检索结果-内蒙古大学图书馆

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第1期22卷 190-195页

作者： James, Alex Pappachen Francis, Linu Rose V. J. Kumar, Dinesh S. Indian Inst Informat Technol & Management Intelligent Machines & Neuromorph Engn Lab Trivandrum 695581 Kerala India

We report a resistance-based threshold logic family useful for mimicking brain-like large variable logic functions in VLSI. A universal boolean logic cell based on an analog resistive divider and threshold logic circuit is presented. The resistive divider is implemented using memristors, and provides output voltage as a summation of weighted product of input voltages. The output of the resistive divider is converted into a binary value by a threshold operation implemented by cmos inverter and/or Opamp. A universal cell structure is presented to decrease the overall implementation complexity and number of components. When the number of input variables becomes very high, the proposed cell offers advantages of smaller area and design simplicity in comparison with cmos-based logic circuits.

关键词： cmos logic circuits memristors resistive circuits threshold logic

来源：评论

学校读者我要写书评

暂无评论

Simple power analysis applied to nonlinear feedback shift registers

引用

IET INFORMATION SECURITY 2014年第3期8卷 188-198页

作者： Zadeh, Abdulah Abdulah Heys, Howard M. Mem Univ Newfoundland St John NF Canada

Linear feedback shift registers (LFSRs) and nonlinear feedback shift register (NLFSRs) are major components of stream ciphers. It has been shown that, under certain idealised assumptions, LFSRs and LFSR-based stream ciphers are susceptible to cryptanalysis using simple power analysis (SPA). In this study, the authors show that SPA can be practically applied to a cmos digital hardware circuit to determine the bit values of an NLFSR and SPA therefore has applicability to NLFSR-based stream ciphers. A new approach is used with the cryptanalyst collecting power consumption information from the system on both edges (triggering and non-triggering) of the clock in the digital hardware circuit. The method is applied using simulated power measurements from an 80-bit NLFSR targeted to an 180 nm cmos implementation. To overcome inaccuracies associated with mapping power measurements to the cipher data, the authors offer novel analytical techniques which help the analysis to find the bit values of the NLFSR. Using the obtained results, the authors analyse the complexity of the analysis on the NLFSR and show that SPA is able to successfully determine the NLFSR bits with modest computational complexity and a small number of power measurement samples.

关键词： cmos logic circuits computational complexity cryptography power aware computing shift registers size 180 nm word length 80 bit computational complexity cipher data simulated power measurements clock edges digital hardware circuit power consumption information LFSR-based stream ciphers NLFSR-based stream ciphers bit value determination cmos digital hardware circuit SPA simple power analysis cryptanalysis stream ciphers nonLFSR LFSR linear feedback shift registers nonlinear feedback shift registers

来源：评论

学校读者我要写书评

暂无评论

Compact inductorless cmos low-noise amplifier for reconfigurable radio

引用

ELECTRONICS LETTERS 2014年第12期50卷 892-893页

作者： Slimane, Abdelhalim Haddad, Fayrouz Bourdel, Sylvain Tedjini-Bailiche, Sid Ahmed Belaroussi, Mohand Tahar Mohamed, Trabelsi Barthelemy, Herve Ctr Dev Technol Avancees Algiers Algeria Aix Marseille Univ IM2NP Marseille France Univ Grenoble Minatec IMEP LAHC F-38000 Grenoble France Ecole Natl Polytech Alger Algiers Algeria

A compact reconfigurable cmos low-noise amplifier (LNA) is presented for applications in DCS1800, UMTS, WLAN-b/g and Bluetooth standards. The proposed LNA features first a current reuse shunt-feedback amplifier for wideband input matching, low-noise figure and small area. Secondly, a cascode amplifier with a tunable active LC resonator is added for high gain and continuous tuning of bands. Fabricated in a 0.13 mu m cmos process, the measured results show >20 dB power gain, <3.5 dB noise figure in the frequency range of 1.8-2.4 GHz, return losses S-11 and S-22 lower than -12 and -14 dB, respectively, with a moderate IIP3 of -11.8 dBm at 2.4 GHz. It consumes 9.6 mW from a 1.2 V supply voltage, while occupying an active silicon area of only 0.052 mm(2).

关键词： TELECOMMUNICATION systems MOBILE communication systems WIRELESS communication systems COMPLEMENTARY metal oxide semiconductors cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

Vedic division methodology for high-speed very large scale integration applications

引用

JOURNAL OF ENGINEERING-JOE 2014年第2期2014卷 51-59页

作者： Saha, Prabir Kumar, Deepak Bhattacharyya, Partha Dandapat, Anup Natl Inst Technol Dept Elect & Commun Engn Shillong 793003 Meghalaya India Natl Inst Technol Dept Comp Sci & Engn Shillong 793003 Meghalaya India Bengal Engn & Sci Univ Dept Elect & Telecommun Engn Sibpur 711103 Howrah India

Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ''Dhvajanka (on top of the flag)' formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 % 16) bit divider circuitry was only similar to 300 ns and consumed similar to 32.5 mW power for a layout area of 17.39 mm2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as similar to 47, similar to 38, 34% reduction in delay and similar to 34, similar to 21, similar to 18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton-Raphson, Goldschmidt) architectures.

关键词： very high speed integrated circuits SPICE cmos logic circuits dividing circuits size 90 nm digit-recurrence architectures Newton-Raphson architectures Goldschmidt architectures cmos technology complementary metal oxide semiconductor technology spice spectre stage reduction divider circuitry dynamic power consumption propagation delay Dhvajanka formula ancient Vedic mathematics transistor level implementation high-speed very large scale integration applications Vedic division methodology

来源：评论

学校读者我要写书评

暂无评论

Modular Layout-friendly Cell Library Design Applied for Subthreshold cmos 32

Modular Layout-friendly Cell Library Design Applied for Subt...

引用

32nd NORCHIP Conference

作者： Bjerkedok, Jonathan Edvard Vatanjou, Ali Asghar Ytterdal, Trond Aunet, Snorre NTNU N-1383 Asker Norway Norwegian Univ Sci & Technol NTNU Dept Elect & Telecommun N-7491 Trondheim Norway

ISBN: (纸本)9781479954421

A new method for designing digital cell libraries is presented where basic building blocks for logic and memory may be built from identical stacks of transistors in series, only, simplifying the design. Simulations in subthreshold operation is included, suggesting that the method could in principle be used for any synchronous finite state machine. A standard 4 transistor implementation and an 8-transistor version using our suggested approach, having equal total areas, are compared using statistical simulations in 65 nm cmos, taking local variations into account. The average standard deviations of circuit delays for the traditional NAND implementation were then less than half ( 44 %), when compared to the new 8 transistor implementation. Anyway, for the same sizing, the traditional NAND2 had about twice the total active area, about 37 % higher static power consumption, 127 % higher active power consumption and about 51 % higher energy per operation, according to simulations. The static power consumption was also about 33 % higher for the traditional NAND, compared to the suggested approach based on combining a couple of 4-transistor "slices". Combining identical "'slices"' of transistors enabling in principle a range of combinatorial and memory building blocks could greatly simplify library cell design, or subsets of cell libraries.

关键词： cmos logic circuits NAND circuits combinational circuits delay circuits finite state machines logic design power consumption statistical analysis transistors NAND implementation NAND2 active power consumption average standard deviations combinatorial building blocks energy per operation identical stacks local variations logic circuit delays memory building blocks modular layout-friendly digital cell library design size 65 nm static power consumption statistical simulations subthreshold cmos operation synchronous finite state machine total active area transistor slices Delays Layout Libraries logic gates Power demand Standards Transistors Transistor Device Component Power consumption NAND circuits finite state machines delay circuits cmos logic circuits Combinational circuits Power demand logic design Libraries logic gates layouts cell library useful area

来源：评论

学校读者我要写书评

暂无评论

Skew Tolerance Analysis and Layout Design of 4x4 multiplier Using Two Phase Clocking Subthreshold Adiabatic logic

Skew Tolerance Analysis and Layout Design of 4x4 multiplier ...

引用

IEEE Asia Pacific Conference on circuits and Systems (APCCAS)

作者： Kato, Kazunari Takahashi, Yasuhiro Sekine, Toshikazu Gifu Univ Grad Sch Engn Gifu Gifu 5011193 Japan Gifu Univ Dept Elect Elect & Comp Engn Fac Engn Gifu Gifu 5011193 Japan

ISBN: (纸本)9781479952304

We have previously proposed a new digital cmos circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic logic circuit. From skew analysis, we see that the proposed circuit correctly operates. Circuit operation and performance is evaluated using a 4x4-bit multiplier fabricated in a 0.18 mu m cmos process. The post layout results show that the multiplier was operated with clock frequencies 1 kHz.

关键词： cmos logic circuits integrated circuit layout multiplying circuits radiofrequency integrated circuits tolerance analysis AC power supply digital cmos circuit frequency 1 kHz layout design multiplier size 0.18 mum skew tolerance analysis two phase clocking subthreshold adiabatic logic circuit ultralow power consumption Arrays cmos integrated circuits Clocks Inverters Layout Switching circuits Timing Multiplying circuits Tolerance analysis alternating current power Timing devices layout design layouts Radio frequency integrated circuits Switched circuits cmos logic circuits integrated circuit layout cmos integrated circuits Inventors Power consumption TWO-PHASE Skew

来源：评论

学校读者我要写书评

暂无评论

Near-threshold voltage operation of a nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

Near-threshold voltage operation of a nonvolatile SRAM cell ...

引用

SOI-3D-Subthreshold Microelectronics Technology Unified Conference

作者： Shuto, Y. Yamamoto, S. Sugahara, S. Tokyo Inst Technol Imaging Sci & Engn Lab Yokohama Kanagawa Japan

ISBN: (纸本)9781479974399

The bias assist techniques and power switch design for stable near-threshold voltage operations of the NV-SRAM cell are investigated. Although the pull-up of VDD is necessary for the store operation, this executes only at the moment of the shutdown of the cell and the energy required for the store operation can be completely compensated by the shutdown during a period prescribed by break-even time [8]. The NV-SRAM cell using PS-FinFETs is promising for the NVPG architecture of near-threshold-voltage cmos logic systems.

关键词： cmos logic circuits cmos memory circuits SRAM chips power MOSFET cmos logic systems bias assist techniques near-threshold voltage operation nonvolatile SRAM cell power switch design pseudospin-FinFET architecture FinFETs Magnetic resonance imaging Magnetic tunneling Standards Static random access storage cmos memory circuits magnetic tunnelling cmos logic circuits store operation Power MESFETs Fin field effect transistors SRAM cells Magnetic Resonance Imaging Cells

来源：评论

学校读者我要写书评

暂无评论

Effectiveness of Dual-Rail CSSAL against Power Analysis Attack under cmos Process Variation

Effectiveness of Dual-Rail CSSAL against Power Analysis Atta...

引用

IEEE Asia Pacific Conference on circuits and Systems (APCCAS)

作者： Monteiro, Cancio Takahashi, Yasuhiro Sekine, Toshikazu Gifu Univ Grad Sch Engn Gifu 5011193 Japan Gifu Univ Fac Engn Gifu 5011193 Japan

ISBN: (纸本)9781479952304

This paper investigates the effectiveness of secure dual-rail adiabatic logic against power analysis attack under cmos process variations. The ability of the previously proposed logic in multiplier over GF(2(4)) is investigated in terms of transitional energy dissipation using 100 data samples from Monte Carlo simulation. The adiabatic multiplier circuits are simulated using 0.18-mu m and 90-nm cmos process at an operating power clock frequency of 12.5MHz. The SPICE simulation results show that the proposed CSSAL multiplier has high stability and strong immunity in consuming constant power than other investigated logic styles.

关键词： cmos logic circuits Monte Carlo methods SPICE clocks power consumption cmos process variation GF Monte Carlo simulation SPICE simulation adiabatic multiplier circuits constant power consumption dual-rail CSSAL effectiveness dual-rail charge-sharing symmetric adiabatic logic style frequency 12.5 MHz operating power clock frequency power analysis attack size 0.18 mum size 90 nm transitional energy dissipation cmos integrated circuits cmos process Circuit stability Cryptography Energy dissipation Semiconductor device modeling Standards Monte Carlo technique cmos process power analysis circuit stability cmos logic circuits Energy dissipation Semiconductor device models SPICE cmos integrated circuits Timing devices cryptography Power consumption Multiplying circuits Formal logic

来源：评论

学校读者我要写书评

暂无评论

Pass-XNOR logic: A new logic Style for P-N Junction based Graphene circuits

Pass-XNOR Logic: A new Logic Style for P-N Junction based Gr...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Tenace, Valerio Calimera, Andrea Macii, Enrico Poncino, Massimo Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

ISBN: (纸本)9783981537024

In this work we introduce a new logic style for p-n junctions based digital graphene circuits: the pass-XNOR logic style. The latter enables the realization of compact, energy efficient circuits that better exploit the characteristics of graphene. We first show how a single p-n junction can be conceived as a pass-XNOR gate, i.e.,a transmission gate with embedded logic functionality, the XNOR Boolean operator. Secondly, we propose a smart integration strategy in which series/parallel connections of pass-XNOR gates allow to implement AND/OR logical conjunctions, and, therefore, all possible truth tables. Experimental results conducted on a set of representative logic functions show the superior of pass-XNOR logic circuits w.r.t. standard cmos circuits and graphene circuits that use p-n junctions in a complementary-like structure.

关键词： cmos logic circuits graphene logic gates p-n junctions AND-OR logical conjunctions cmos circuits XNOR Boolean operator complementary-like structure embedded logic functionality energy efficient circuits p-n junctions based digital graphene circuits pass-XNOR logic style smart integration strategy transmission gate truth tables cmos integrated circuits Doping Graphene logic functions logic gates P-n junctions

来源：评论

学校读者我要写书评

暂无评论

High-Performance III-V devices for future logic applications 60

High-Performance III-V devices for future logic applications

引用

60th Annual IEEE International Electron Devices Meeting (IEDM)

作者： Kim, D. -H. Kim, T. -W. Baek, R. H. Kirsch, P. D. Maszara, W. del Alamo, J. A. Antoniadis, D. A. Urteaga, M. Brar, B. Kwon, H. M. Shin, C. -S. Park, W. -K. Cho, Y. -D. Shin, S. H. Ko, D. H. Seo, K. -S. SEMATECH Albany NY 12203 USA GLOBALFOUNDRIES Milpitas CA USA MIT Cambridge MA 02139 USA Teledyne Sci Thousand Oaks CA USA KANC Carroll County NH USA Yonsei Univ Seoul 120749 South Korea Seoul Natl Univ Seoul 151 South Korea

ISBN: (纸本)9781479980000

High-mobility III-V transistors are poised to take the lead on future high performance logic operation. If this happens, indium-rich InxGa1-xAs is the most promising n-channel material. Indeed, remarkable progress has been made, including III-V gate-stacks with ALD-grown gate dielectrics. This paper reviews the evolution of high-performance III-V devices for future logic applications and discuss a possible path forward to further improve their logic figure-of-merits.

关键词： cmos logic circuits III-V semiconductors gallium arsenide indium compounds logic devices ALD-grown gate dielectrics III-V devices III-V gate-stacks InxGa1-xAs high-mobility III-V transistors logic applications logic figure-of-merits logic operation n-channel material HEMTs Hafnium oxide Indium gallium arsenide logic gates MODFETs MOSFET Silicon

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：