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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是131-140 订阅

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Standard cmos Voltage-mode QLUT Using a Clock Boosting Technique

Standard CMOS Voltage-mode QLUT Using a Clock Boosting Techn...

引用

11th IEEE International New circuits and Systems Conference (NEWCAS)

作者： Brito, Diogo Fernandes, Jorge Flores, Paulo Monteiro, Jose Univ Tecn Lisboa INESC ID Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781479906208

Interconnect has become preponderant in many aspects of digital circuit design, namely delay, power and area. This effect is particularly true for FPGAs, where interconnection is often the most limiting factor. Multiple-valued logic allows to reduce interconnections, within logic cells and between them, hence effectively mitigating the impact of interconnections. In this paper we propose a new look-up table structure based on a low-power high-speed quaternary voltage-mode device. Our quaternary implementation overcomes the drawbacks of previously proposed techniques by using a standard cmos technology and a clock boosting technique to enhance speed without increasing consumption. Moreover, we present an ASIC prototype of a full adder based on the designed look-up table and experimental results are obtained and compared with simulation. The prototype is designed to work at 100 MHz and it consumes 128 mu W.

关键词： cmos logic circuits adders application specific integrated circuits clocks field programmable gate arrays integrated circuit interconnections logic design multivalued logic table lookup

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TSV Count Minimization And Thermal Analysis for 3D Tree-based FPGA

TSV Count Minimization And Thermal Analysis for 3D Tree-base...

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International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Pangracious, Vinod Mehrez, Habib Marakchi, Zied Univ Paris 06 LIP6 F-75006 Paris France FlexRas Technol Paris France

ISBN: (纸本)9781467347433

The cmos technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due the programming overhead of FPGA. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. Through Silicon Vias (TSV) provide electrical connectivity between multiple active device planes in 3D integrated circuits (ICs). TSVs require a significant silicon area compared to planar interconnects and also bring critical challenges to design of 3D ICs. In this paper we propose an architectural level TSV count optimization solution to minimize, the TSV count without compromising the chip performance. TSVs are also used very effectively to control the increase in inter-layer temperature of 3D ICs. We propose a TSV based 3D thermal optimization model for FPGA. The experimental results shows our methodology is able to reduce 35% of the total TSV count in 3D Tree-based FPGA.

关键词： cmos logic circuits application specific integrated circuits elemental semiconductors field programmable gate arrays silicon thermal analysis three-dimensional integrated circuits

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Design of a (255,239) Reed-Solomon Decoder Using a Simplified Step-by-Step Algorithm

Design of a (255,239) Reed-Solomon Decoder Using a Simplifie...

引用

IEEE 17th International Symposium on Consumer Electronics (ISCE)

作者： Su, Yu-Shan Yu, Chu Lin, Bor-Shing Cheng, Po-Hsun Chen, Sao-Jie Natl ILan Univ Dept Elect Engn Yilan Taiwan Natl Taipei Univ Dept Comp Sci & Informat Engn Taipei Taiwan Natl Kaohsiung Normal Univ Dept Software Engn Kaohsiung Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan

ISBN: (纸本)9781467361996

This paper presents the design of a new (255, 239) Reed-Solomon (RS) decoder using a simplified step-by-step algorithm. For calculating the syndrome determinant in the RS decoder, the proposed architecture performs Gauss elimination on a 1-D systolic array that has lower hardware complexity and is more suited to be used on a higher-dimension matrix with the step-by-step algorithm. The proposed architecture, designed in 0.18 mu m cmos technology, has approximately 25K gates, and consumes approximately 40 mW at 250 MHz.

关键词： cmos logic circuits Gaussian processes Reed-Solomon codes decoding systolic arrays

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Design and Verification of an All-Digital On-Chip Process Variation Sensor

Design and Verification of an All-Digital On-Chip Process Va...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Oh, Reum Jang, Ji Woong Sung, Man Young Korea Univ Seoul South Korea

ISBN: (纸本)9781467357623;9781467357609

This paper presents a process variation sensing circuit technique for maintaining the performance benefit of cmos digital circuits and reducing variations in delay and robustness. The new process sensor consists of two inverter chains with different loading capacitances and a time-to-digital converter (TDC) that detects delay variations between the inverter chains. Results based on the measured TDC data are used to adjust the supply voltages of systems to optimal values. This technique considerably saves power in digital circuits and increases yield in high performance bins. In order to verify the operation and performance of the novel sensor, an all-digital delay-locked-loop (DLL) was designed and its jitter was measured. The circuits, which were fabricated with a 0.13um cmos process, showed the 20% improved jitter variations compared with a conventional DLL without process compensation.

关键词： cmos logic circuits delay lock loops electric sensing devices logic gates time-digital conversion

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61 pJ/sample Near-Threshold Notch Filter with Pole-Radius Variation

61 pJ/sample Near-Threshold Notch Filter with Pole-Radius Va...

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IEEE 4th Latin American Symposium on circuits and Systems (LASCAS)

作者： Soares, Leonardo Stangherlin, Kleber de Mello, Jorge Bampi, Sergio Univ Fed Rio Grande do Sul Inst Informat PGMicro Porto Alegre RS Brazil

ISBN: (纸本)9781424494859;9781467348973

This paper presents results of digital cmos design for ultra-low power filter that uses logic cells operating at near-threshold voltage supplies. The cells were designed in 65 nm cmos technology for ultra-low power. The hardware implementation of a pole-radius-varying Infinite Impulse Response (IIR) notch filter is addressed. Previous works have shown that digital design of pole-radius-varying (or Q factor-varying) IIR notch filters can suppress the transient effect. The proposed filter is synthesized using our custom 65 nm near-threshold voltage standard cells library. Comparisons from near-threshold operation to nominal voltages show large gains in energy-savings for this filter that make the logic architecture suitable for sub-nano-Joule per sample applications.

关键词： cmos logic circuits IIR filters integrated circuit design low-power electronics notch filters

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DIFFERENTIAL HIGH SPEED ULTRA LOW-VOLTAGE PASS TRANSISTOR BOOLEAN logic

DIFFERENTIAL HIGH SPEED ULTRA LOW-VOLTAGE PASS TRANSISTOR BO...

引用

IEEE Faible Tension Faible Consommation Conference (FTFC)

作者： Berg, Y. Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781467361040;9781467361057

In this paper we present high-speed and ultra low-voltage pass transistor. The delay of the proposed pass transistors are less than 6% of conventional cmos pass transistors operating at supply voltages down to 200mV. The pass transistor logic presented can be used to implement low-voltage high-speed serial adders. The simulated data provided is obtained using Cadence and 90nm TSMC cmos process.

关键词： cmos logic circuits MOSFET adders circuit simulation low-power electronics

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Maximizing Yield in Near-Threshold Computing under the Presence of Process Variation

Maximizing Yield in Near-Threshold Computing under the Prese...

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23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

作者： Conos, Nathaniel A. Meguerdichian, Saro Wei, Sheng Potkonjak, Miodrag Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781479911707

Near-Threshold Computing (NTC) shows potential to provide significant energy efficiency improvements as it alleviates the impact of leakage in modern deep sub-micron cmos technology. As the gap between supply and threshold voltage shrink, however, the energy efficiency gains come at the cost of device performance variability. Thus, adopting near-threshold in modern CAD flows requires careful consideration when addressing commonly targeted objectives. We propose a process variation-aware near-threshold voltage (PV-N-vt) gate sizing framework for minimizing power subject to performance yield constraints. We evaluate our approach using an industrial-flow on a set of modern benchmarks. Our results show our method achieves significant improvement in leakage power, while meeting performance yield targets, over a state-of-the-art method that does not consider near-threshold computing.

关键词： cmos logic circuits energy conservation integrated circuit yield leakage currents logic CAD logic design logic gates power aware computing

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FinPrin: Analysis and Optimization of FinFET logic circuits under PVT Variations

<i>FinPrin</i>: Analysis and Optimization of FinFET Logic Ci...

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26th International Conference on VLSI Design Held Concurrently with 12th International Conference on Embedded Systems Design

作者： Yang, Yang Jha, Niraj K. Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9780769548890;9781467349208

Continued scaling of bulk cmos technology is facing formidable challenges. As an alternative, FinFETs offer a promising solution for the 22nm technology node and beyond though they still suffer from process, voltage, and temperature (PVT) variations. Thus, in order to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis (STA). In this paper, we consider voltage and temperature variations in addition to process variations. We propose a simplified FinFET timing model with an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared to accurate quasi Monte-Carlo (QMC) simulations. We extend an existing SSTA algorithm to statistical leakage and dynamic power analysis as well, and evaluate its performance relative to Monte-Carlo (MC) simulation. Finally, we show that FinFET logic circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

关键词： cmos logic circuits MOSFET Monte Carlo methods delay circuits logic gates scaling circuits statistical analysis timing circuits

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Ultra Low Power Pulse Generator Based on a Ring Oscillator with Direct Path Current Avoidance

Ultra Low Power Pulse Generator Based on a Ring Oscillator w...

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IEEE 4th Latin American Symposium on circuits and Systems (LASCAS)

作者： Veirano, Francisco Perez, Pablo Besio, Sebastian Castro, Pablo Silveira, Fernando Univ Republica Inst Ingn Elect Fac Ingn Montevideo Uruguay

ISBN: (纸本)9781424494859;9781467348973

This paper presents a wide frequency range, ultra low power pulse generator based on a ring oscillator. The proposed architecture avoids the direct path current, reaching pulse frequencies down to the kHz range while maintaining the power consumption proportional to frequency. Furthermore, the used topology for the current starved inverter circuit improves the symmetry between rising and falling edges of the output signals of the ring oscillator with respect to the traditional implementation. A frequency range from 1.75kHz to 10MHz consuming 1nW and 3.6 mu W respectively was achieved in a 130nm cmos process. The modular design can be used to generate any non- overlapping pulse sequence with variable width.

关键词： cmos logic circuits integrated circuit design logic design logic gates oscillators pulse generators

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A 1/4-inch 8Mpixel Back-Illuminated Stacked cmos Image Sensor

A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Senso...

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IEEE International Solid-State circuits Flagship Conference of the IEEE Solid-State-circuits-Society (ISSCC)

作者： Sukegawa, Shunichi Umebayashi, Taku Nakajima, Tsutomu Kawanobe, Hiroshi Koseki, Ken Hirota, Isao Haruta, Tsutomu Kasai, Masanori Fukumoto, Koji Wakano, Toshifumi Inoue, Keishi Takahashi, Hiroshi Nagano, Takashi Nitta, Yoshikazu Hirayama, Teruo Fukushima, Noriyuki Sony Corp Atsugi Kanagawa Japan Sony LSI Design Atsugi Kanagawa Japan Sony Semicond Kumamoto Japan

ISBN: (纸本)9781467345132;9781467345156

In recent years, cellphone cameras have come to require much more diversification and increased functionalities, due to the strong growth of the smartphone market. In addition to the image quality, speed, and pixel counts that conventional image sensors require, there is high demand for new functions that can respond to various photo-taking scenes. We developed a stacked cmos image sensor (CIS), composed of conventional back-illuminated (BI) image-sensor technology and 65nm standard logic technology.

关键词： cmos image sensors cmos logic circuits mobile handsets

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