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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是141-150 订阅

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HIGH SPEED ULTRA LOW-VOLTAGE DIFFERENTIAL D FLIP-FLOP FOR LOW-VOLTAGE cmos DESIGN

HIGH SPEED ULTRA LOW-VOLTAGE DIFFERENTIAL D FLIP-FLOP FOR LO...

引用

IEEE Faible Tension Faible Consommation Conference (FTFC)

作者： Berg, Y. Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781467361040;9781467361057

In this paper we present a novel differential cmos D Flip-Flop based on a high-current pass transistor. We use floating capacitors to obtain a current boost at specific events, i.e clock edges. The Flip-Flop presented may be used inany low voltage digital cmos systems. The delay is reduced to approximately 12% compared to a conventional sense. amplifier differential Flip-Flop. The simulated data provided is obtained using Cadence and 90nm TSMC cmos process.

关键词： cmos logic circuits flip-flops high-speed integrated circuits logic design

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Robustness-Driven Energy-Efficient Ultra-Low Voltage Standard Cell Design with Intra-Cell Mixed-V_t Methodology

Robustness-Driven Energy-Efficient Ultra-Low Voltage Standar...

引用

ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)

作者： Zhao, Wenfeng Ha, Yajun Hoo, Chin Hau Alvarez, Anastacia B. Natl Univ Singapore Dept Elect & Comp Engn Singapore 117548 Singapore

ISBN: (纸本)9781479912346;9781479912353

High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-V-t design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm cmos process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.

关键词： cmos logic circuits integrated circuit design logic design logic gates

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Investigating the Behavior of Physical Defects in pn-Junction Based Reconfigurable Graphene Devices

Investigating the Behavior of Physical Defects in pn-Junctio...

引用

14th IEEE Latin-American Test Workshop (LATW)

作者： Miryala, Sandeep Calimera, Andrea Macii, Enrico Poncino, Massimo Poehls, Leticia Bolzani Politecn Torino I-10129 Turin Italy

ISBN: (纸本)9781479905973;9781479905959

Graphene, one of the viable candidates to replace Silicon in the next generation electronic devices, is pushing the research community to find new technological solutions that can exploit its special characteristics. Among the proposed approaches, the electrostatic doping represents a key option. It allows the implementation of equivalent pn-junctions through which is possible to build a new class of reconfigurable logic gates, the devices analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. cmos technologies below the 22nm. This work explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, has been analyzed and mapped at a higher level of abstraction using proper fault models. Most of such models belong to the cmos domain, but for some specific class of defects, new fault definitions are needed.

关键词： cmos logic circuits SPICE graphene logic gates p-n junctions semiconductor doping

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Automatic Place&Route of Nano-Magnetic logic circuits

Automatic Place&Route of Nano-Magnetic Logic Circuits

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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Vacca, M. Frache, S. Graziano, M. Di Crescenzo, L. Cairo, F. Zamboni, M. Politecn Torino Dipartimento Elettron & Telecomunicaz Turin Italy

ISBN: (纸本)9781479908738;9781479908745

The analysis of effective expectations on emerging nanotechnologies, like Nano-magnetic logic, is currently a difficult task. The lack of tools that enable the design at logic and physical level of nano-circuits does not allow to inspect properties that can be derived only considering circuits of reasonable complexity. We present results of an unprecedented Place & Route engine for Nano-magnetic logic, integrated in our tool for nanotechnologies design exploration. We developed and compared several algorithms to tackle Nano-magnetic logic constraints and limitations, derived by real-life technological implementations, on complex combinational circuits (ISCAS85 benchmarks) and show to what extent Nano-Magnetic logic can advance cmos.

关键词： cmos logic circuits nanomagnetics

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A New Design Technique for Low Power Subthreshold logic circuits with Enhanced Robustness Against Process Variations

A New Design Technique for Low Power Subthreshold Logic Circ...

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21st Iranian Conference on Electrical Engineering (ICEE)

作者： Majidi, Sareh Maymandi-nejad, Mohammad Ferdowsi Univ Mashhad Mashhad Iran

ISBN: (纸本)9781467356343

Designing logic circuits in the subthreshold regime is one of the most effective ways to reduce the power consumption of digital circuits. In the subthreshold region, the current is an exponential function of the threshold voltage and the behavior of transistors is more susceptible to process variations. In this paper, we present a new design technique that helps reduce the impact of process variations on the circuit. The proposed technique is implemented on the staticC2MOS flip-flop and the flip flop is used in a shift register. The circuit is simulated in the 90nm cmos technology using a 0.2V supply voltage. Simulation results show that the robustness of the circuit is improved while the power consumption and the area are kept at minimum.

关键词： cmos logic circuits flip-flops logic design low-power electronics

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Novel MTJ-Based Shift Register for Non-Volatile logic Applications

Novel MTJ-Based Shift Register for Non-Volatile Logic Applic...

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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Windbacher, Thomas Mahmoudi, Hiwa Sverdlov, Viktor Selberherr, Siegfried TU Wien Inst Microelect Gusshausstr 27-29E360 A-1040 Vienna Austria

ISBN: (纸本)9781479908738;9781479908745

The increasing costs and leakage losses have become the major concerns for cmos technology scaling. A possible way to address in particular the standby power problem is to introduce non-volatility into the devices and circuit blocks so that unused devices or even entire circuit blocks do not waste energy, and power is only spent, when information is read or written. Recently, we proposed a non-volatile magnetic flip flop which moves the information storage and processing from the cmos domain to the magnetic domain. Here, we propose a way to extend the functionality of the device to a shift register;computing via spin wave superposition and passing information by spin torque transfer (STT). The presented shift register and its operation allows an extremely dense layout, is cmos compatible, and non-volatile.

关键词： cmos logic circuits flip-flops magnetic tunnelling shift registers

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An Ultra-Low-Power Voltage-Mode Asynchronous WTA-LTA Circuit

An Ultra-Low-Power Voltage-Mode Asynchronous WTA-LTA Circuit

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Fernandez-Berni, Jorge Carmona-Galan, Ricardo Rodriquez-Vazquez, Angel CSIC Inst Microelect Seville IMSE CNM C Americo Vespucio S-N Seville 41092 Spain

ISBN: (纸本)9781467357623;9781467357609

This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimum-maximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard cmos base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.

关键词： cmos logic circuits asynchronous circuits image processing mixed analogue-digital integrated circuits parallel architectures three-dimensional integrated circuits

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A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm cmos

A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded ...

引用

35th Annual IEEE Custom Integrated circuits Conference (CICC) - The Showcase for Circuit Design in the Heart of Silicon Valley

作者： Nam, Jae-Won Chiong, David Chen, Mike Shuo-Wei Univ So Calif Los Angeles CA 90089 USA

ISBN: (纸本)9781467361460

An 11b asynchronous successive approximation register analog to digital converter with embedded passive gain architecture is proposed and prototyped in 65nm cmos. The proposed passive gain technique is integrated in the sampling capacitor network as part of the SAR conversion, and provides a signal gain of 2x prior to the comparator without consuming static current. It thus reduces the comparator noise impact as well as enhancing the overall ADC conversion speed and power efficiency. The ADC prototype demonstrates a peak SNDR of 63.1dB and SFDR of 75.2dB when sampling at 95MS/s. Both measured differential and integral nonlinearities of the prototype are less than 0.84 LSB. It occupies an active area of 0.073mm(2) and dissipates 1.36mW from 1.1V supply. Keywords: analog-to-digital, SAR, sub-radix.

关键词： cmos logic circuits analogue-digital conversion asynchronous circuits embedded systems integrated circuit noise low-power electronics

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Low-Complexity Layered Iterative Hard-Reliability-Based Majority-logic Decoder for Non-Binary Quasi-Cyclic LDPC Codes

Low-Complexity Layered Iterative Hard-Reliability-Based Majo...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiong, Chenrong Yan, Zhiyuan Lehigh Univ Dept Elect & Comp Engn Bethlehem PA 18015 USA

ISBN: (纸本)9781467357623;9781467357609

Non-binary low-density parity-check (NB-LDPC) codes have some advantages as opposed to their binary counter-parts, but unfortunately their decoding complexity is a significant challenge. Hence, iterative hard-reliability-based majority-logic decoding (IHRB-MLGD) algorithms are attractive for NB-LDPC codes due to their low complexities. In this paper, we propose a layered improved iterative hard-reliability-based majority-logic decoding algorithm and design a partly parallel architecture for the proposed algorithm. Our improved algorithm achieves better error performance and faster convergence than existing IHRB-MLGD algorithms, while maintaining low complexities. The proposed partly parallel architecture achieves a throughput of 779 Mbps with SMIC 0.13um cmos technology.

关键词： cmos logic circuits computational complexity cyclic codes iterative decoding parallel architectures parity check codes reliability

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Novel redundant logic design for noisy low voltage scenarios

Novel redundant logic design for noisy low voltage scenarios

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IEEE 4th Latin American Symposium on circuits and Systems (LASCAS)

作者： Garcia-Leyva, Lancelot Calomarde, Antonio Moll, Francesc Rubio, Antonio Univ Autonoma Tlaxcala Fac Ciencias Basicas Ingn & Tecnol Apizaco 90300 Tlaxcala Mexico

ISBN: (纸本)9781424494859;9781467348973

The concept worked in this paper named Turtle logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging cmos technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard cmos techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 degrees C and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.

关键词： AWGN cmos logic circuits integrated circuit reliability logic design logic gates

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