检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,880 篇 会议
644 篇 期刊文献
3 篇 学位论文

馆藏范围

4,527 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,168 篇 工学
- 821 篇 电气工程
- 351 篇 电子科学与技术（可...
- 247 篇 计算机科学与技术...
- 51 篇 材料科学与工程（可...
- 51 篇 控制科学与工程
- 50 篇 核科学与技术
- 36 篇 信息与通信工程
- 30 篇 软件工程
- 25 篇 机械工程
- 24 篇 仪器科学与技术
- 4 篇 生物医学工程（可授...
- 3 篇 光学工程
- 1 篇 力学（可授工学、理...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 交通运输工程
- 1 篇 网络空间安全
100 篇 理学
- 77 篇 物理学
- 18 篇 系统科学
- 6 篇 化学
- 1 篇 生物学
27 篇 管理学
- 27 篇 管理科学与工程(可...
5 篇 医学
- 4 篇 临床医学
- 1 篇 基础医学(可授医学...
- 1 篇 特种医学
3 篇 教育学
- 3 篇 教育学
1 篇 文学
- 1 篇 新闻传播学
1 篇 艺术学
- 1 篇 设计学（可授艺术学...

主题

4,527 篇 cmos logic circu...
1,837 篇 cmos technology
997 篇 logic circuits
899 篇 logic design
782 篇 clocks
773 篇 voltage
721 篇 logic devices
640 篇 logic gates
633 篇 cmos process
609 篇 energy consumpti...
518 篇 circuit simulati...
504 篇 delay
500 篇 very large scale...
499 篇 circuit testing
447 篇 switches
420 篇 semiconductor de...
410 篇 power dissipatio...
365 篇 threshold voltag...
361 篇 logic testing
339 篇 mosfets

机构

48 篇 ibm thomas j. wa...
25 篇 faculty of infor...
22 篇 texas instrument...
21 篇 department of el...
17 篇 central research...
17 篇 department of el...
16 篇 philips research...
16 篇 department of el...
15 篇 department of in...
14 篇 school of electr...
14 篇 intel corporatio...
14 篇 infineon technol...
13 篇 department of el...
13 篇 massachusetts in...
12 篇 lsi logic corpor...
12 篇 department of el...
12 篇 department of el...
10 篇 intel corporatio...
10 篇 semiconductor de...
10 篇 imec leuven

作者

37 篇 k. roy
25 篇 jianping hu
18 篇 m. hashizume
18 篇 m.i. elmasry
17 篇 y. berg
16 篇 j.b. kuo
16 篇 t. tamesada
15 篇 c. sechen
13 篇 d. al-khalili
13 篇 k.w. current
13 篇 s. vassiliadis
12 篇 kuo-hsing cheng
12 篇 sung-mo kang
12 篇 m. shams
12 篇 yusuf leblebici
11 篇 a. afzali-kusha
11 篇 f. matsuoka
11 篇 n.k. jha
11 篇 e.j. mccluskey
11 篇 j. figueras

语言

4,435 篇 英文
51 篇 其他
41 篇 中文

检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是151-160 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Nonvolatile logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating

Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS ...

引用

IEEE International Solid-State circuits Flagship Conference of the IEEE Solid-State-circuits-Society (ISSCC)

作者： Natsui, Masanori Suzuki, Daisuke Sakimura, Noboru Nebashi, Ryusuke Tsuji, Yukihide Morioka, Ayuka Sugibayashi, Tadahiko Miura, Sadahiko Honjo, Hiroaki Kinoshita, Keizo Ikeda, Shoji Endoh, Tetsuo Ohno, Hideo Hanyu, Takahiro Tohoku Univ Sendai Miyagi 980 Japan NEC Corp Ltd Tsukuba Ibaraki Japan

ISBN: (纸本)9781467345132;9781467345156

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a cmos logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

关键词： cmos logic circuits MRAM devices VLSI field programmable gate arrays magnetic tunnelling video coding

来源：评论

学校读者我要写书评

暂无评论

Biomimetic Non-linear cmos Adder for Neuromorphic circuits

Biomimetic Non-linear CMOS Adder for Neuromorphic Circuits

引用

6th International IEEE EMBS Conference on Neural Engineering (NER)

作者： Zhou, Xiahan Guo, Yimu Parker, Alice C. Hsu, Chih-Chieh Choma, John Univ So Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467319690

This paper presents a novel biomimetic cmos two-input non-linear adder circuit to fully emulate computations within dendritic branches of pyramidal neurons. It automatically and dynamically adjusts neuron responses based on the input magnitudes of EPSP potentials. The design is based on cmos 180nm technology with dual power supplies.

关键词： cmos logic circuits adders biomimetics neural chips

来源：评论

学校读者我要写书评

暂无评论

A 7-bit 50MS/s Single-ended Asynchronous SAR ADC in 65nm cmos

A 7-bit 50MS/s Single-ended Asynchronous SAR ADC in 65nm CMO...

引用

NORCHIP Conference

作者： Xu, Ye Ytterdal, Trond Norwegian Univ Sci & Technol Dept Elect & Telecommun Trondheim Norway

ISBN: (纸本)9781479916474

This paper presents a 7-bit 50MS/s single-ended asynchronous SAR ADC intended for in-probe use in some ultrasound imaging system. It aims at low power, small area and moderate resolution. Relaxed by a moderate resolution, a single-ended architecture with a double reference technique is proposed to improve the power efficiency and reduce active area, which are limited by the minimum dimension of the technology. Also, a delay line with tunable and asymmetric characteristics is proposed to be embedded in the asynchronous digital logic, enabling high speed at 50MS/s. Simulations show that the prototype designed in a 65nm cmos technology achieves an SNDR of 42.7dB and an ENOB of 6.8bit at a sampling frequency of 50MS/s while consuming 157 mu W from a 1V supply, resulting in an energy efficiency of 28fJ/conversion-step. The core circuit layout only occupies 0.017mm(2).

关键词： cmos logic circuits analogue-digital conversion asynchronous circuits delay lines integrated circuit design low-power electronics ultrasonic imaging

来源：评论

学校读者我要写书评

暂无评论

A Process-Variation Compensation Scheme to Operate cmos Digital logic Cells in Deep Sub-Threshold Region at 80mV

A Process-Variation Compensation Scheme to Operate CMOS Digi...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Kappel, Robert Auer, Mario Pribyl, Wolfgang Hofer, Guenter Holweg, Gerald Graz Univ Technol Inst Elect A-8010 Graz Austria Infineon Technol Austria AG Dev Ctr Graz Graz Austria

ISBN: (纸本)9781467357623;9781467357609

In this paper a simple technique to use standard digital cmos logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic's switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

关键词： cmos logic circuits NAND circuits NOR circuits compensation flip-flops logic testing

来源：评论

学校读者我要写书评

暂无评论

Design of a Low-Power Pulse-Triggered Flip-Flop with Conditional Clock Technique

Design of a Low-Power Pulse-Triggered Flip-Flop with Conditi...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiang, Guang-Ping Shen, Ji-Zhong Wu, Xue-Xiang Geng, Liang Zhejiang Univ Inst Elect Circuits & Informat Syst Hangzhou 310003 Zhejiang Peoples R China

ISBN: (纸本)9781467357623;9781467357609

Flip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is designed. In CCFF, the clock is blocked when the input remains unchanged so that the internal nodes will not switch with the clock, which reduces the power consumption effectively. Based on the TSMC 0.18 mu m technology, the post-layout simulation results show that the proposed CCFF has an obvious advantage in power consumption when the data switching activity factor is below 50% as compared with other state-of-the-art pulse-triggered flip-flops, and the power saving is more than 50% when the activity factor is 10%.

关键词： cmos logic circuits clocks flip-flops logic design low-power electronics

来源：评论

学校读者我要写书评

暂无评论

Transistor-Level Optimization of cmos Complex Gates

Transistor-Level Optimization of CMOS Complex Gates

引用

IEEE 4th Latin American Symposium on circuits and Systems (LASCAS)

作者： Possani, Vinicius N. Marques, Felipe S. da Rosa Junior, Leomar S. Callegaro, Vinicius Reis, Andre I. Ribas, Renato P. Fed Univ Pelotas UFPel Grp Architectures & Integrated Circuits Pelotas Brazil

ISBN: (纸本)9781424494859;9781467348973

This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating cmos logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.

关键词： Boolean functions cmos logic circuits integrated circuit design logic design logic gates

来源：评论

学校读者我要写书评

暂无评论

A 0.18V Charge-Pumped DFF with 50.8% Energy-Delay Reduction for Near-/Sub-threshold circuits

A 0.18V Charge-Pumped DFF with 50.8% Energy-Delay Reduction ...

引用

9th IEEE Asian Solid-State circuits Conference (A-SSCC)

作者： Wang, Bo Zhou, Jun Chang, Kah Hyong Je, Minkyu Kim, Tony T. Nanyang Technol Univ VIRTUS Sch Elect & Elect Engn Singapore 639798 Singapore ASTAR Inst Microelect Singapore Singapore

ISBN: (纸本)9781479902774;9781479902804

This paper presents a 16-transistor charge-pumped DFF featuring a low energy-delay product for near-/subthreshold applications. The device count of the proposed DFF is minimized by eliminating clock buffer and employing pass gates instead of transmission gates. To reduce the Clock-to-Q delay and improve variation resilience, two charge pumps and an anti-inverse-narrow-width-effect strategy are utilized, improving the performance by 23%. The proposed DFF is fully functional down to 0.18V and shows the energy-delay product of 13.1 *** at 100% data activity, achieving 51.8% improvement compared to the conventional TGFF. When VDD=0.5V, the energy-delay product is averagely enhanced by 50.8%. Two 256-bit FIFOs are implemented in 180nm cmos technology using the proposed DFF and TGFF. The FIFO utilizing the charge-pumped DFF exhibits 31.2% total power reduction at subthreshold regime.

关键词： cmos logic circuits charge pump circuits flip-flops

来源：评论

学校读者我要写书评

暂无评论

An Analytical Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies

An Analytical Model of the Overshooting Effect for Multiple-...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Ding, Li Wang, Jing Huang, Zhangcai Kurokawa, Atsushi Inoue, Yasuaki Waseda Univ Grad Sch Informat Prod & Syst Wakamatsu Ku 2-7 Hibikino Kitakyushu Fukuoka 8080135 Japan Hirosaki Univ Grad Sch Sci & Technol Hirosaki Aomori 036 Japan

ISBN: (纸本)9781467357623;9781467357609

The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on cmos gate delay with the scaling of cmos technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.

关键词： cmos logic circuits integrated circuit modelling logic gates nanoelectronics

来源：评论

学校读者我要写书评

暂无评论

Aging-aware logic Synthesis

Aging-aware Logic Synthesis

引用

32nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Ebrahimi, Mojtaba Oboril, Fabian Kiamehr, Saman Tahoori, Mehdi B. Karlsruhe Inst Technol Chair Dependable & Nano Comp D-76021 Karlsruhe Germany

ISBN: (纸本)9781479910717

As cmos technology scales down into the nanometer regime, designers have to add pessimistic timing margins to the circuit as guardbands to avoid timing violations due to various reliability effects, in particular accelerated transistor aging. Since aging is workload-dependent, the aging rates of different paths are non-uniform, and hence, design time delay-balanced circuits become significantly unbalanced after some operational time. In this paper, an aging-aware logic synthesis approach is proposed to increase circuit lifetime with respect to a specific guardband. Our main objective is to optimize the design timing with respect to post-aging delay in a way that all paths reach the assigned guardband at the same time. In this regard, in an iterative process, after computing the post-aging delays, the lifetime is improved by putting tighter timing constraints on paths with higher aging rate and looser constraints on paths which have less post-aging delay than the desired guarband. The experimental results shows that the proposed approach improves circuit lifetime in average by more than 3X with negligible impact on area. Our approach is implemented on top of a commercial synthesis toolchain, and hence scales very well.

关键词： cmos logic circuits circuit optimisation iterative methods logic design

来源：评论

学校读者我要写书评

暂无评论

Gate Stack Resistance and Limits to cmos logic Performance

Gate Stack Resistance and Limits to CMOS Logic Performance

引用

35th Annual IEEE Custom Integrated circuits Conference (CICC) - The Showcase for Circuit Design in the Heart of Silicon Valley

作者： Wachnik, R. A. Lee, S. Pan, L. H. Lu, N. Li, H. Bingert, R. Randall, M. Springer, S. Putnam, C. IBM Semicond Res & Dev Ctr Essex Jct VT 05452 USA IBM Semicond Res & Dev Ctr Hopewell Jct NY 12533 USA ST Microelect Hopewell Jct NY 12533 USA

ISBN: (纸本)9781467361460

The input resistance of cmos circuits is a measurable limit on the performance of typical static cmos logic gates. A survey of measured data from five generations of cmos technology including polysilicon oxynitride gate first stacks (P-SiON), high-K metal gate first stacks (GF), and high-K replacement metal gate stacks (RMG) shows a trend of increasing gate resistance. We show DC and RF measurements may be analyzed to determine horizontal and vertical components of gate resistance in terms of scalable parameters and the sum of these components may be represented by a compact scalable equation representing total gate resistance. Gate resistance increases at advanced nodes and affects typical logic performance of a 20nm replacement gate technology.

关键词： cmos logic circuits high-k dielectric thin films integrated circuit measurement logic gates

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共453页 << < 12 13 14 15 16 17 18 19 20 21 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：