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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是161-170 订阅

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Ultra-Low Voltage and High Speed NP Domino Carry Propagation chain

Ultra-Low Voltage and High Speed NP Domino Carry Propagation...

引用

IEEE Faible Tension Faible Consommation Conference (FTFC)

作者： Mahmood, Sohail Musa Berg, Yngvar Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781467361040;9781467361057

In this paper, an Ultra Low Voltage NP domino logic style is presented to perform a 32 bit computation in a carry propagation chain. The presented logic style is targeted to operate at the supply voltages near the sub-threshold regime. Simulated results of 32-bit proposed carry chain compared to the conventional carry chain conclude that the proposed approach offers a superb improvement in terms of speed and EDP. The proposed carry chain has a relative delay and EDP of only 2.68% and 8% respectively compared to the conventional carry chain. The 32-bit ULV NP domino carry chain using 90nm TSMC cmos process technology with a supply voltage of 300mV could be operated at a clock frequency of 50MHz.

关键词： cmos logic circuits carry logic high-speed integrated circuits logic design

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An Energy Efficient Approximate Adder with Carry Skip for Error Resilient Neuromorphic VLSI Systems 13

An Energy Efficient Approximate Adder with Carry Skip for Er...

引用

32nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Kim, Yongtae Zhang, Yong Li, Peng Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781479910717

We propose a novel approximate adder design to significantly reduce energy consumption with a very moderate error rate. The significantly improved error rate and critical path delay stem from the employed carry prediction technique that leverages the information from less significant input bits in a parallel manner. An error magnitude reduction scheme is proposed to further reduce amount of error once detected with low cost. Implemented in a commercial 90 nm cmos process, it is shown that the proposed adder is up to 2.4x faster and 43% more energy efficient over traditional adders while having an error rate of only 0.18%. The proposed adder has been adopted in a VLSI-based neuromorphic character recognition chip using unsupervised learning. The approximation errors of the proposed adder have been shown to have negligible impact on the training process. Moreover, the energy savings of up to 48.5% over traditional adders is achieved for the neuromorphic circuit with scaled supply level. Finally, we achieve error-free operations by including a low-overhead error correction logic.

关键词： cmos logic circuits VLSI adders approximation theory logic design neural nets unsupervised learning

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Scan-Controlled Pulse Flip-Flops for Mobile Application Processors

Scan-Controlled Pulse Flip-Flops for Mobile Application Proc...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Kim, Min-su Lee, HyoungWook Park, Jin-Soo Kim, Chung-Hee Kang, Juhyun Shin, Ken Kagramanyan, Emil Jung, Gunok Cho, Ukrae Shin, Youngmin Son, Jae Cheol Samsung Elect Yongin 449711 Kyunggi Do South Korea

ISBN: (纸本)9781467357623;9781467357609

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm cmos process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

关键词： cmos logic circuits flip-flops low-power electronics

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Low Power Secure AES S-Box using Adiabatic logic Circuit

Low Power Secure AES S-Box using Adiabatic Logic Circuit

引用

IEEE Faible Tension Faible Consommation Conference (FTFC)

作者： Monteiro, Cancio Takahashi, Yasuhiro Sekine, Toshikazu Gifu Univ Grad Sch Engn 1-1 Yanagido Gifu 5011193 Japan Gifu Univ Fac Engn Gifu 5011193 Japan

ISBN: (纸本)9781467361040;9781467361057

Numerous works on advanced encryption standard (AES) S-box architecture have been done using composite field arithmetic in Galois field. However, to the best of our knowledge, less information is available on both a secure circuit and the low power consumption. In this work, we implement our previous proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using multi-stage positive polarity Reed-Muller (PPRM) representation over composite field technique. The logic sharing method for frequently same logic function usage in the combination logic is applied. Consequently, the low-complexity, high resistive and the low-power consumption are achieved. The results in this paper are obtained from the SPICE simulation with 0.18-mu m 1.8-V standard cmos technology at operating frequency of 1.25-70 MHz. Base on the logic speed, security performance and low-power requirement, we deduce that our proposed logic is applicable for contactless smart cards, RFID tags, and wireless sensors.

关键词： cmos logic circuits Galois fields Reed-Muller codes combinational circuits cryptography power consumption radiofrequency identification smart cards

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Reliability analysis of combinational circuits with the influences of noise and single-event transients

Reliability analysis of combinational circuits with the infl...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

作者： Liu, Kaikai Cai, Hao An, Ting Naviner, Lirida Naviner, Jean-Francois Petit, Herve TELECOM ParisTech LTCI CNRS Inst Mines TELECOM 46 Rue Barrault F-75013 Paris France

ISBN: (纸本)9781479915859;9781479915835

Noise-immunity is an important design criterion with cmos dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

关键词： cmos logic circuits SPICE combinational circuits integrated circuit noise integrated circuit reliability mathematics computing radiation hardening (electronics) transients

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Low Power Sub-Threshold Asynchronous QDI Static logic Transistor-level Implementation (SLTI) 32-Bit ALU

Low Power Sub-Threshold Asynchronous QDI Static Logic Transi...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Ho, Weng-Geng Chong, Kwen-Siong Gwee, Bah-Hwee Chang, Joseph S. Nanyang Technol Univ Singapore 639798 Singapore

ISBN: (纸本)9781467357623;9781467357609

We propose an asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) Static logic Transistor-level Implementation (SLTI) approach for low power sub-threshold operation. The approach is implemented to design 32-bit pipelined Arithmetic and logic Units (ALUs), the primary computation core for microprocessors, and benchmarked against the reported Pre-Charged Half-Buffer (PCHB). There are two key attributes in this proposed design. First, the proposed SLTI ALU design can perform dynamic voltage scaling seamless by only changing the supply voltage from nominal (1V) to subthreshold (similar to 0.2V) regions for high speed/low power operation. Second, the ALU achieves ultra-low power dissipation (3.5 mu W) at the lowest V-DD point (similar to 0.15V). For fair of comparison, both implemented ALUs have identical functionality and functional blocks, are implemented using the same 65nm cmos process. Based on the simulations, the minimum energy point occurs at V-DD = 0.2V for SLTI-based ALU and at V-DD = 0.3V for PCHB-based ALU. The SLTI-based ALU have similar to 93% and similar to 89% lower energy on the arithmetic and logic operations respectively from V-DD = 1V to V-DD = 0.2V. At V-DD = 0.2V, with 9MHz input switching rate, the async ALU based on our proposed SLTI approach dissipates similar to 51% and similar to 44% lower power than the reported PCHB counterpart on the arithmetic and logic operations respectively.

关键词： cmos logic circuits asynchronous sequential logic low-power electronics microprocessor chips power aware computing

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A cmos FIELD PROGRAMMABLE ANALOG ARRAY FOR INTELLIGENT SENSORY APPLICATION

A CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR INTELLIGENT SENSO...

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23rd International Conference on Field Programmable logic and Applications (FPL)

作者： Cheng, Xiaoyan Yin, Tao Wu, Qisong Jia, Yiping Yang, Haigang Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China

ISBN: (纸本)9781479900046

A Field-Programmable Analog Array (FPAA) architecture designed for intelligent sensory application is presented, which consists of high performance and high flexible Configurable Analog Blocks (CABs). The CAB is developed to realize both continuous-time and discrete-time circuits for achieving optimal performance in different applications. In addition to employ coarse-grained reconfigurable CAB in FPAA, a fine-grained reconfigurable amplifier in the CAB is utilized to maximize programmability and flexibility. The precision of the analog processing is enhanced by employing fat-tree interconnection network topology to minimize the number of switches used in FPAA and using correlated double sampling (CDS) techniques to suppress the offset and noise. The FPAA is designed and implemented in SMIC 0.18 mu m cmos process with a 3.3 V supply voltage. An instrumental amplifier and a capacitive sensor signal readout circuit are taken as application examples. The relative precision and dynamic range of the analog processing are 97.6% and 119dB respectively.

关键词： cmos logic circuits analogue processing circuits field programmable gate arrays instrumentation amplifiers intelligent sensors logic design

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Tunable cmos Delay Gate with Reduced Impact of Fabrication Mismatch on Timing Parameters

Tunable CMOS Delay Gate with Reduced Impact of Fabrication M...

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11th IEEE International New circuits and Systems Conference (NEWCAS)

作者： Mroszczyk, Przemyslaw Dudek, Piotr Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England

ISBN: (纸本)9781479906208

This paper presents the analysis and design of a simple one-stage tunable delay gate with improved matching properties as compared with the commonly used "current starved inverter". The operation of two delay lines employing these structures in a standard 90 nm cmos technology was verified based on the post layout mismatch Monte Carlo simulations. Accounting for the fabrication mismatch, the delay generated by the proposed "output-split inverter" (OSI) circuit is about 10-30% more accurate as compared to the conventional current starved inverter occupying the same chip area.

关键词： cmos logic circuits Monte Carlo methods delay lines integrated circuit layout logic design logic gates

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Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design

Analysis and Comparison of XOR Cell Structures for Low Volta...

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14th International Symposium on Quality Electronic Design (ISQED)

作者： Nishizawa, Shinichi Ishihara, Tohru Onodera, Hidetoshi Kyoto Univ Grad Sch Informat Sakyo Ku Kyoto 6068501 Japan

ISBN: (纸本)9781467349529;9781467349512

The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary cmos logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary cmos XOR in 0.6V operation, while the complementary cmos XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary cmos XOR in 0.6V operation.

关键词： cmos logic circuits benchmark testing integrated circuit design low-power electronics

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Low Power Multi-Lane MIPI CSI-2 Receiver Design and Hardware Implementations 17th

Low Power Multi-Lane MIPI CSI-2 Receiver Design and Hardware...

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IEEE 17th International Symposium on Consumer Electronics (ISCE)

作者： Lu, Yueh-Chuan Chen, Zong-Yi Chang, Pao-Chi Student Member IEEE Member IEEE

ISBN: (纸本)9781467361996

This paper proposes a low power multi-Lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) receiver architecture which adopts an 8-Byte parallel CSI protocol layer for hardware implementations. The proposed scheme can work in environment with 4 data Lanes and 1 Gb/s per data Lane, i.e. with maximum data rate 4 Gb/s, at 62.5 MHz which increases logic operations from 8 ns (125 MHz) to 16 ns (62.5 MHz) without throughput degradation. Therefore, the supply voltage (1.2 V) can be reduced and the power consumption can also be reduced. The proposed architecture is implemented by 0.13 mu m cmos technology and the total gate count is 32.7K. It not only reduces the operating clock rate but also reduces more than 37%similar to 43% logic power consumption measured in chip.

关键词： cmos logic circuits cameras mobile radio parallel architectures peripheral interfaces power consumption radio receivers

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