检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,880 篇 会议
644 篇 期刊文献
3 篇 学位论文

馆藏范围

4,527 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,168 篇 工学
- 821 篇 电气工程
- 351 篇 电子科学与技术（可...
- 247 篇 计算机科学与技术...
- 51 篇 材料科学与工程（可...
- 51 篇 控制科学与工程
- 50 篇 核科学与技术
- 36 篇 信息与通信工程
- 30 篇 软件工程
- 25 篇 机械工程
- 24 篇 仪器科学与技术
- 4 篇 生物医学工程（可授...
- 3 篇 光学工程
- 1 篇 力学（可授工学、理...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 交通运输工程
- 1 篇 网络空间安全
100 篇 理学
- 77 篇 物理学
- 18 篇 系统科学
- 6 篇 化学
- 1 篇 生物学
27 篇 管理学
- 27 篇 管理科学与工程(可...
5 篇 医学
- 4 篇 临床医学
- 1 篇 基础医学(可授医学...
- 1 篇 特种医学
3 篇 教育学
- 3 篇 教育学
1 篇 文学
- 1 篇 新闻传播学
1 篇 艺术学
- 1 篇 设计学（可授艺术学...

主题

4,527 篇 cmos logic circu...
1,837 篇 cmos technology
997 篇 logic circuits
899 篇 logic design
782 篇 clocks
773 篇 voltage
721 篇 logic devices
640 篇 logic gates
633 篇 cmos process
609 篇 energy consumpti...
518 篇 circuit simulati...
504 篇 delay
500 篇 very large scale...
499 篇 circuit testing
447 篇 switches
420 篇 semiconductor de...
410 篇 power dissipatio...
365 篇 threshold voltag...
361 篇 logic testing
339 篇 mosfets

机构

48 篇 ibm thomas j. wa...
25 篇 faculty of infor...
22 篇 texas instrument...
21 篇 department of el...
17 篇 central research...
17 篇 department of el...
16 篇 philips research...
16 篇 department of el...
15 篇 department of in...
14 篇 school of electr...
14 篇 intel corporatio...
14 篇 infineon technol...
13 篇 department of el...
13 篇 massachusetts in...
12 篇 lsi logic corpor...
12 篇 department of el...
12 篇 department of el...
10 篇 intel corporatio...
10 篇 semiconductor de...
10 篇 imec leuven

作者

37 篇 k. roy
25 篇 jianping hu
18 篇 m. hashizume
18 篇 m.i. elmasry
17 篇 y. berg
16 篇 j.b. kuo
16 篇 t. tamesada
15 篇 c. sechen
13 篇 d. al-khalili
13 篇 k.w. current
13 篇 s. vassiliadis
12 篇 kuo-hsing cheng
12 篇 sung-mo kang
12 篇 m. shams
12 篇 yusuf leblebici
11 篇 a. afzali-kusha
11 篇 f. matsuoka
11 篇 n.k. jha
11 篇 e.j. mccluskey
11 篇 j. figueras

语言

4,435 篇 英文
51 篇 其他
41 篇 中文

检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Impact of Random Telegraph Noise on cmos logic Delay Uncertainty under Low Voltage Operation

Impact of Random Telegraph Noise on CMOS Logic Delay Uncerta...

引用

IEEE International Electron Devices Meeting (IEDM)

作者： Matsumoto, Takashi Kobayashi, Kazutoshi Onodera, Hidetoshi Kyoto Univ Dept Commun & Comp Engn Kyoto Japan Kyoto Inst Technol Dept Elect Kyoto Japan

ISBN: (纸本)9781467348706;9781467348720

Statistical nature of RTN-induced delay fluctuation is described by measuring 2,520 ROs fabricated in a commercial 40 nm cmos technology. Small number of samples have a large RTN-induced delay fluctuation. RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V). By slightly increasing the transistor size, more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation. The impact of the parameters that can be changed by circuit designers is clarified in view of RTN-induced cmos logic delay uncertainty.

关键词： cmos logic circuits delay circuits

来源：评论

学校读者我要写书评

暂无评论

Highly Digitalized Flash Analog to Digital (FADC) Converter using Mux Based Decoder Topology

Highly Digitalized Flash Analog to Digital (FADC) Converter ...

引用

IEEE 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking

作者： Palsodkar, Prachi Dakhole, Pravin Palsodkar, Prasanna Kale, Ashwini V. Yeshwantrao Chavan Coll Engg Dept Elect Engn Nagpur Maharashtra India

ISBN: (纸本)9781467316286;9781467316262

In this paper Flash ADC (FADC) is Implemented in 0.18 mu m technology using cmos Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design of low power high speed FADC. Presence of bubble error reduces output correction capability. An advanced scheme is proposed for correction of bubble error in Mux based decoder. FADC comparators designed with systematic sizing of transistors where linearity measures of convertor include 0.42 LSB INL, +0.62/-0.75 LSB DNL and ENOB 3.09 at 20MHz.

关键词： cmos logic circuits analogue-digital conversion binary codes comparators (circuits) decoding ladder networks logic gates

来源：评论

学校读者我要写书评

暂无评论

First Demonstration of logic Mapping on Nonvolatile Programmable Cell Using Complementary Atom Switch

First Demonstration of Logic Mapping on Nonvolatile Programm...

引用

IEEE International Electron Devices Meeting (IEDM)

作者： Miyamura, M. Tada, M. Sakamoto, T. Banno, N. Okamoto, K. Iguchi, N. Hada, H. Low Power Elect Assoc & Project LEAP Tsukuba Ibaraki 3058569 Japan

ISBN: (纸本)9781467348706;9781467348720

Reconfigurable nonvolatile programmable logic using complementary atom switch (CAS) is successfully demonstrated on a 65-nm-node test chip. Various logics are realized by synthesizing RTL codes and mapping the configurations into CAS-based programmable cell array. Each cell includes the two 4-input LUTs, 19x16 crossbar switch, and 368-b CAS. The CAS integrated over cmos reduces the cell area by 78% compared to a conventional SRAM-based design.

关键词： cmos logic circuits programmable logic arrays switches table lookup

来源：评论

学校读者我要写书评

暂无评论

A Process-Compatible Passive RFID Tag's Digital Design for Subthreshold Operation

A Process-Compatible Passive RFID Tag's Digital Design for S...

引用

19th IEEE International Conference on Electronics, circuits, and Systems (ICECS 2012)

作者： Shi, Weiwei Choy, Chiu-Sing Shenzhen Univ Coll Informat Engn Shenzhen Peoples R China Shenzhen Key Lab Modern Commun & Informat Proc Shenzhen Peoples R China Chinese Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781467312608

Based on deep submicron cmos technologies and limit power availability, a low-power subthreshold passive UHF RFID tag's digital design is presented in this paper. The design uses specific techniques for ultra-low-voltage condition, addressing the long logic propagation time and wide-range-variation problems. According to the EPC C1G2 protocol, compensated addition is proposed in PIE decoding, and power-aware scheme is applied to the entire architecture. Additionally, double-edge-triggered technique helps to improve clock efficiency, reducing the complexity and power of the tag's clock generator. Galoi linear feedback shift register (LFSR) and one-hot counter are applied to meet the critical timing requirements in command handling blocks. To ensure the compatibility, the baseband processor was fabricated in 180nm, 130nm and 90nm cmos technologies respectively, and the logic designs indicate good robustness in very-low supply voltage testing. Minimum operating voltages are at least 70 mV lower than the regular threshold voltage.

关键词： cmos logic circuits cryptographic protocols decoding integrated circuit design logic design radiofrequency identification shift registers

来源：评论

学校读者我要写书评

暂无评论

Estimating the starting point of conduction in nano-scale cmos gates

Estimating the starting point of conduction in nano-scale CM...

引用

19th IEEE International Conference on Electronics, circuits, and Systems (ICECS 2012)

作者： Tzagkas, Dimitrios Nikolaidis, Spyridon Rjoub, Abdoul Aristotle Univ Thessaloniki Dept Phys Thessaloniki Greece Jordan Univ Sci & Technol Dept Comp Engn Irbid Jordan

ISBN: (纸本)9781467312608

In this paper a method for calculating the starting point of conduction of parallel and serial transistor structures in cmos gates for the nanoscale regime is introduced. The calculation of the starting point is necessary for modeling the operation of complex gates. The influence of the parasitic capacitances is determined and the subthreshold and conducting behavior of the transistors are considered for the analysis of the operation of the serial transistor structure. Appropriate assumptions are used for modeling the circuit operation whose efficiency is determined by the accuracy of the results compared to HSPICE simulations. The overall accuracy of the proposed method is verified through HSPICE simulations for 32nm high k dielectric PTM technology.

关键词： cmos logic circuits MOSFET high-k dielectric thin films logic gates nanoelectronics

来源：评论

学校读者我要写书评

暂无评论

Towards High Mobility GeSn Channel nMOSFETs: Improved Surface Passivation Using Novel Ozone Oxidation Method

Towards High Mobility GeSn Channel nMOSFETs: Improved Surfac...

引用

IEEE International Electron Devices Meeting (IEDM)

作者： Gupta, S. Vincent, B. Yang, B. Lin, D. Gencarelli, F. Lin, J. -Y. J. Chen, R. Richard, O. Bender, H. Magyari-Koepe, B. Caymax, M. Dekoster, J. Nishi, Y. Saraswat, K. C. Stanford Univ Dept Elect Engn Stanford CA 94305 USA IMEC B-3001 Louvain Belgium Katholieke Univ Leuven B-3001 Louvain Belgium GLOBAL FOUNDRIES Sunnyvale CA 94085 USA

ISBN: (纸本)9781467348706;9781467348720

We present a detailed theoretical analysis to motivate GeSn for cmos logic. High quality GeSn films have been obtained on Ge-on-Si using a CVD process. A novel surface passivation scheme is presented to achieve record low trap densities at high-K/GeSn interface. Using the novel surface passivation method, combined with a low thermal budget device fabrication process, n-channel MOSFETs on GeSn with channel Sn content as high as 8.5% have been demonstrated for the first time.

关键词： cmos logic circuits MOSFET chemical vapour deposition germanium compounds high-k dielectric thin films oxidation ozonation (materials processing) passivation semiconductor thin films

来源：评论

学校读者我要写书评

暂无评论

Yield-Driven Minimum Energy cmos Cell Design

Yield-Driven Minimum Energy CMOS Cell Design

引用

46th Asilomar Conference on Signals, Systems and Computers

作者： Korbel, Max A. Stow, Dylan C. Ferguson, Chris R. Harris, David Money Harvey Mudd Coll Claremont CA 91711 USA

ISBN: (纸本)9781467350518

cmos circuits operating near or below threshold offer the lowest energy per computation. Previous work reduces the total energy by using minimum sizing and lowering the voltage without concern for yield. To achieve better yield, the voltage or size must increase. The minimum energy point for minimum-sized NAND2 gates in a 65 nm process is 0.475 V consuming 0.0275 fJ/cycie with a gate failure rate of 2x10(-4). However, to achieve a failure rate of 10(-6), minimum energy is achieved by widening pMOS transistors by 50%, increasing total energy by 11.9%, which is 7.2% better than minimum width devices and higher voltage.

关键词： cmos logic circuits MOSFET failure analysis logic gates

来源：评论

学校读者我要写书评

暂无评论

Anti-Resonance Peak Damping of PDN Impedance by On-board Snubber circuits

Anti-Resonance Peak Damping of PDN Impedance by On-board Snu...

引用

IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

作者： Iijima, You Matsumura, Masataka Sudo, Toshio Shibaura Inst Technol Koto Ku Tokyo 108 Japan

ISBN: (纸本)9781467314442;9781467314459

Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced cmos circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.

关键词： cmos logic circuits damping electric impedance electromagnetic interference field programmable gate arrays network analysis on-board communications power supplies to apparatus snubbers

来源：评论

学校读者我要写书评

暂无评论

A New XOR-Based Content Addressable Memory Architecture

A New XOR-Based Content Addressable Memory Architecture

引用

19th IEEE International Conference on Electronics, circuits, and Systems (ICECS 2012)

作者： Frontini, Luca Shojaii, Seyedruhollah Stabile, Alberto Liberali, Valentino Univ Milan Dept Phys Via Celoria 16 I-20133 Milan Italy

ISBN: (纸本)9781467312608

In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-cmos combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.

关键词： cmos logic circuits SRAM chips content-addressable storage logic gates

来源：评论

学校读者我要写书评

暂无评论

Does PMOS Vth Shift Wholly Capture the Degradation of cmos Inverter Circuit under DC NBTI?

Does PMOS Vth Shift Wholly Capture the Degradation of CMOS I...

引用

IEEE International Integrated Reliability Workshop (IIRW)

作者： Chenouf, Amel Djezzar, Boualem Benabedelmoumene, Abdelmadjid Tahi, Hakim CDTA Adv Technol Dev Ctr Microelect & Nanotechnol Div Algiers 16303 Algeria

ISBN: (纸本)9781467327527;9781467327497

In this paper, an experimental investigation of negative bias temperature instability (NBTI) impact on cmos inverter circuit is presented. The study focuses on the contribution of NBTI induced PMOS V-th shift on the degradation of the circuit DC features. This investigation was conducted in order to understand the origin of performance shifts due to NBTI at the circuit level and to properly predict the lifetime of the inverter circuit. The experimental setup was based on a measure/stress/measure procedure, where a series of negative gate voltages at different temperatures were applied via an automated test bench to the circuit under test. The results we obtained show, on one side, the cmos inverter voltage transfer curve (VTC) shifts under NBTI stress to the left side, as predicted by the theory. This shift implies a shift of the critical logic voltages of the inverter. On the other side, the analysis of the logic threshold shift with respect to the inverter's PMOS threshold voltage shift shows clearly, and contrary to predicted by theory, that PMOS threshold voltage (V-th) shift does not wholly capture the degradation of the cmos inverter logic threshold shift. In fact, this later is found to be affected by both PMOS and NMOS V-th shifts. Therefore, it cannot be unconditionally assumed that the effect of NBTI on cmos circuits could be exclusively predicted by only shifting the PMOS V-th.

关键词： cmos logic circuits integrated circuit reliability logic gates logic testing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共453页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：