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Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第6期4卷 499-514页

作者： Esmaeili, S. E. Al-Khalili, A. J. Cowan, G. E. R. Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE- SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

关键词： power consumption logic and switching circuits STMicroelectronics 90 nm technology transistors clock distribution networks resonant clock signal emerging resonant clocking technique precharging transistors Pulse circuits size 90 nm Semiconductor integrated circuit design, layout, modelling and testing logic circuits cmos logic circuits dual edge triggered sense amplifier flip-flop integrated circuit layout resonant clock distribution networks trigger circuits frequency 500 MHz cmos integrated circuits distributed amplifiers circuit layout flip-flops short circuit power reduction

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A Reconfigurable Neural Spike Recording Channel with Feature Extraction Capabilities

A Reconfigurable Neural Spike Recording Channel with Feature...

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Biomedical circuits and Systems Conference (BioCAS)

作者： Rodriguez-Perez, Alberto Ruiz-Amaya, Jesus Guerra, Oscar Delgado-Restituto, Manuel CSIC CNM Inst Microelect Seville IMSE Edificio IMSE CNMAvda Americo Vespucio S-N Seville 41092 Spain Univ Seville Seville 41092 Spain

ISBN: (纸本)9781424472703

This paper describes the architecture of a neural spike recording channel with feature extraction capabilities and presents the design of one of its key elements, a reconfigurable 8bit ADC. The ADC can be programmed for different conversion rates and embeds a 0-18dB programmable gain amplifier with discrete gain steps of 3dB. Simulation results from extracted layout of the ADC, designed in a 130nm cmos technology, obtain almost 8-bit ENOB at 22.2kS/s and 90kS/s, with a power consumption of 500nW and 1.8 mu W, respectively.

关键词： cmos analogue integrated circuits cmos logic circuits cmos technology analog-to-digital converter analogue-digital conversion biomedical electronics biomedical equipment body sensor networks brain brain activity acquisition feature extraction feature extr

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A Novel Cylinder-Type MIM Capacitor in Porous Low-k Film (CAPL) for Embedded DRAM with Advanced cmos logics

A Novel Cylinder-Type MIM Capacitor in Porous Low-k Film (CA...

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International Electron Devices Meeting (IEDM)

作者： Hijioka, K. Inoue, N. Kume, I. Kawahara, J. Furutake, N. Shirai, H. Itoh, T. Ogura, T. Kazama, K. Yamamoto, Y. Kasama, Y. Katsuyama, H. Manabe, K. Yamamoto, H. Saito, S. Hase, T. Hayashi, Y. Renesas Elect Corp LSI Res Lab Chuo Ku 1120 Shimokuzawa Kanagawa 2525298 Japan Renesas Elect Corp Product & Tech Unit Chuo Ku Kanagawa 2525298 Japan

ISBN: (纸本)9781424474196

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

关键词： cmos logic circuits cmos logics DRAM chips MIM devices SiOCH bypass-contacts capacitors carbon copper interconnect cylinder-type MIM capacitor cylinder-type metal-insulator-metal capacitor embedded DRAM gas-phase deposition hydrogen low-k dielectric thin

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Wafer Scale Fabrication of Carbon Nanotube FETs with Embedded Poly-gates

Wafer Scale Fabrication of Carbon Nanotube FETs with Embedde...

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International Electron Devices Meeting (IEDM)

作者： Han, Shu-Jen Chang, Josephine Franklin, Aaron D. Bol, Ageeth A. Loesing, Rainer Guo, Dechao Tulevski, George S. Haensch, Wilfried Chen, Zhihong IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA IBM Corp SRDC Hopewell Jct NY 12533 USA

ISBN: (纸本)9781424474196

One critical factor that determines the feasibility of employing carbon nanotubes as channel materials for post-silicon logic devices is the process compatibility to the current cmos process flow. We show a wafer-scale integration scheme of carbon nanotube field-effect transistor (CNFET) that is performed by 8" production tools. High density CNT arrays were transferred on the processed wafer, and high performance CNFET with an excellent subthreshold slope (88 mV /decade) is demonstrated. We further show that the work-function tuning enabled by the conventional gate doping can be achieved in our novel embedded poly-Si gate structure. Approximate V-t change of 0.6V, from n-gate to p-gate, is observed. The V-t shift being smaller than the gate work function difference can be attributed to the Fermi level pinning between poly-Si and high-k interface.

关键词： C cmos logic circuits cmos process flow CNFET Fermi level pinning Si carbon nanotube FET carbon nanotube field-effect transistor carbon nanotubes circuit tuning elemental semiconductors embedded polygates field effect transistors gate doping gate work fun

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ULTRA LOW VOLTAGE AND HIGH SPEED cmos FLIP-FLOP USING FLOATING-GATES

ULTRA LOW VOLTAGE AND HIGH SPEED CMOS FLIP-FLOP USING FLOATI...

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Berg, Y. Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781424464708

In this paper we present a novel ultra-low-voltage (ULV) cmos flip-flop (FF) exploiting ULV semi-floating cmos logic. The ULV gates applied offer increased speed compared to other cmos logic styles for low supply voltages. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary cmos gate operating at the same supply voltage. The ULV FF may operate at supply voltages down to 150mV. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm cmos process.

关键词： cmos logic circuits Cadence Spectre simulator ULV semifloating cmos logic flip-flops floating-gates high speed cmos flip-flop size 90 nm ultra-low-voltage cmos flip-flop voltage 150 mV

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A low power, high performance threshold logic-based standard cell multiplier in 65 nm cmos

A low power, high performance threshold logic-based standard...

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IEEE Annual Symposium on VLSI (ISVLSI)

作者： Leshner, Samuel Berezowski, Krzysztof Yao, Xiaoyin Chalivendra, Gayathri Patel, Saurabh Vrudhula, Sarma Arizona State Univ Tempe AZ 85287 USA TIMA Lab Grenoble France

ISBN: (纸本)9780769540764

In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2's complement integer multiplier constructed from a combination of cmos standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using cmos standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.

关键词： cmos logic circuits cmos standard cells high performance logic design logic testing low leakage low power multiplier multiplying circuits standard cell threshold logic threshold logic threshold logic-based standard cell multiplier

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NOVEL ULTRA LOW-VOLTAGE AND HIGH SPEED DOMINO cmos logic

NOVEL ULTRA LOW-VOLTAGE AND HIGH SPEED DOMINO CMOS LOGIC

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Berg, Y. Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781424464708

In this paper we propose a novel ultra low-voltage and high speed domino cmos logic style. The proposed logic style utilizes floating-gate transistors which are used to increase the current level of the transistors driving the output of the gates. In this way the delay of the proposed logic style may be reduced to less than 10% compared to standard cmos.

关键词： cmos logic circuits floating-gate transistors high speed domino cmos logic ultra low-voltage domino cmos logic

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SEU-hardened Dual Data Rate Flip-Flop Using C-elements

SEU-hardened Dual Data Rate Flip-Flop Using C-elements

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25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

作者： Devarapalli, Srikanth V. Zarkesh-Ha, Payman Suddarth, Steven C. Xilinx Albuquerque NM 87109 USA Univ New Mexico Elect & Comp Engn Albuquerque NM 87131 USA COSMIAC Albuquerque NM USA

ISBN: (纸本)9780769542430

Aggressive device scaling has reduced the gate capacitance, which resulted in increasing sensitivity to radiation induced soft errors. In addition, technology scaling has reached to the point of maximum clock frequency to maintain acceptable energy consumption. On the other hand, technology advancements are demanding higher throughput and data rates. To mitigate these problems, we propose a unique single event upset (SEU) hardened dual data rate (DDR) flip-flop using c-elements, "Firebird". Unlike the existing rad-hard flip-flops, the proposed Firebird design not only is truly protected to SEUs, but it also latches in both rising and falling edges of the clock for DDR operation. With the use of DDR, the clock frequency (activity) can be reduced by 2x with no impact on performance. In comparison with the simplified Built-in Soft Error Resilient Flip-Flop (B-SER-FF) with DDR at 45nm cmos process, the proposed Firebird design consumes 19.6% less power, with 9.5% high C2Q delay. The power-delay product of the proposed Firebird design is 11.2% better than its counterpart, B-SER-FF with DDR.

关键词： C-element cmos logic circuits cmos process DDR operation Dual data rate flip-flop SEU hardened flip-flop c-elements Firebird clock frequency data rates delays device scaling energy consumption flip-flops gate capacitance logic design power-delay product radiation induced soft errors single event upset single event upset hardened dual data rate flip-flop size 45 nm

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Magnetic Tunnel Junction for Nonvolatile cmos logic

Magnetic Tunnel Junction for Nonvolatile CMOS Logic

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International Electron Devices Meeting (IEDM)

作者： Ohno, Hideo Endoh, Tetsuo Hanyu, Takahiro Kasai, Naoki Ikeda, Shoji Tohoku Univ Ctr Spintron Integrated Syst Aoba Ku Sendai Miyagi 9808577 Japan

ISBN: (纸本)9781424474196

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronic device, is capable of fast-read/write with high endurance together with back-end-of-the-line (BEOL) compatibility, offering a possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also low-power high-performance nonvolatile cmos logic employing logic-in-memory architecture. The advantages of employing MTJs with cmos circuits are discussed and the current status of the MTJ technology is presented along with its prospect and remaining challenges.

关键词： BEOL compatibility cmos logic circuits MTJ device RAM back-end-of-the-line compatibility logic-in-memory architecture magnetic tunnel junction magnetic tunnelling magnetoelectronics nonvolatile cmos logic nonvolatile spintronic device random-access storag

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From The Future Si Technology Perspective: Challenges and Opportunities

From The Future Si Technology Perspective: Challenges and Op...

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International Electron Devices Meeting (IEDM)

作者： Kim, Kinam Samsung Elect Co SAIT Yongin Gyunggi Do South Korea

ISBN: (纸本)9781424474196

As silicon technology enters sub-20nm nodes, new materials, structures and processes are being introduced in order to continue with the advantages of dimensional scaling, e. g, 3D NAND, ReRAM, EUVL, etc. Beyond 10 nm, Si cmos technology will remain as the mainstream. In this paper, key drivers for silicon-based nano-electronics as well as research directions will be reviewed from viewpoints of system, memory, logic and emerging Si technologies.

关键词： 3D NAND cmos logic circuits cmos memory circuits EUVL ReRAM Si dimensional scaling elemental semiconductors nanoelectronics silicon silicon cmos technology silicon-based nanoelectronics

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