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检索条件"主题词=CMOS Logic Circuits"

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VLSI design of HW/SW interface logic in FC-2

VLSI design of HW/SW interface logic in FC-2

引用

International Conference on Green circuits and Systems (ICGCS)

作者： Jie Jin Xiaoxin Cui Dunshan Yu Peking University Beijing Beijing CN Institute of Microelectronics Peking University Beijing China

In this paper, we propose and compare two architectures of HW/SW interface logic in FC-2, namely as TX/RX scheduler and TX/RX controller. The comparison result shows that the TX/RX controller is more efficient than the TX/RX scheduler. The TX/RX controller is implemented in the proto Fiber Channel (FC) chip fabricated in a 0.18um cmos technology with six layers of metal. The gate count of TX/RX controller is about 10887 gates and the highest throughput of FC chip is 173MBps. In order to further improve the performance of FC, we propose an improved TX/RX controller based on the implemented one. The two interface logics are thoroughly tested in different test cases and the result shows that the improved one can improve the performance by 2~5 times at the cost of 1.8 times area increased.

关键词： Very large scale integration logic design cmos technology cmos logic circuits logic testing Assembly Open systems Multicast protocols Random access memory Optical buffering

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A new 8V – 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

A new 8V – 60V rated low Vgs NLDMOS structure with enhanced...

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： Choul-Joo Ko Cheol-Ho Cho Hee-Bae Lee Yong-Jun Lee Min-Woo Kim Sun-Kyung Bang Han-Geon Kim Jae-O Lee Sang-Chul Shim Sun Kyoung Kang Nam-Joo Kim Kwang-Dong Yoo Lou N. Hutter Analog Foundry Process Development Team Dongbu Hitek Company Limited Bucheon Gyeonggi South Korea

ISBN: (纸本)9781424477180

We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V cmos. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is compatible with the conventional BCDMOS. The power LDMOS transistors in the process have very competitive performances with NLDMOS in 0.15 - 0.25um BCDMOS technologies.

关键词： cmos logic circuits cmos process cmos technology Voltage Charge pumps Implants Driver circuits cmos integrated circuits Doping Power semiconductor devices

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Interconnection of binary and ternary cmos digital circuits and systems

Interconnection of binary and ternary CMOS digital circuits ...

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Proceedings of the International Convention MIPRO

作者： Zlatko Bundalo Dušanka Bundalo Ferid Softić Miroslav Kostadinović Faculty of Electrical Engineering University of Banja Luka Banja Luka Bosnia and Herzegovina UniCredit Bank Banja Luka Bosnia and Herzegovina Faculty of Traffic and Transportation University of East Sarajevo Doboj Bosnia and Herzegovina

Possibilities of synthesis and realization of cmos logic circuits that perform signal conversion from binary to ternary digital system are considered and proposed in the paper. The circuits are used for interconnection of binary and ternary (with logic basis of 3) cmos circuits and systems. General principle of synthesis is proposed and described first. Then, the concrete schemes for synthesis and realization of such circuits are given and described. All given solutions, descriptions and considerations were confirmed by computer simulations. Some results obtained by the simulations are given in the paper.

关键词： Integrated circuit interconnections cmos digital integrated circuits Digital circuits cmos logic circuits Circuit synthesis Signal synthesis Digital systems Multivalued logic circuits and systems Concrete

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Body bias driven design synthesis for optimum performance per area

Body bias driven design synthesis for optimum performance pe...

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IEEE International Symposium on Quality Electronic Design

作者： Maurice Meijer Jose Pineda de Gyvez NXP Semiconductors Eindhoven Netherlands Technical University Eindhoven Eindhoven Netherlands

ISBN: (纸本)9781424464548

Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital cmos IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65 nm LP-cmos, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.

关键词： Circuit synthesis Circuit optimization cmos logic circuits Delay Timing Costs Design optimization Process design Dynamic voltage scaling Frequency

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Low power 4-bit full adder cells in subthreshold regime

Low power 4-bit full adder cells in subthreshold regime

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Iranian Conference on Electrical Engineering (ICEE)

作者： Nayereh Ghobadi Rabe'eh Majidi Mahdieh Mehran Ali Afzali-Kusha School of Electrical and Computer Engineering University of Tehran Tehran Iran

ISBN: (纸本)9781424467600

In this work, low power 4-bit adder cells based on subthreshold logic in nanometer cmos technology is presented. Twelve different subthreshold 1-bit full adders are used for designing 4-bit adders in two different topologies. These topologies are Carry-Ripple and Carry Look-Ahead adders. To compare these adders, HSpice simulations in 65nm and 90nm standard cmos technologies are used. Different performance parameters of the adder including power, delay, power-delay product and energy-delay product as a function of supply voltage, transistor sizing, frequency, technology, and temperature are investigated. The best adder with the smallest power and power-delay product and the highest achievable frequency is determined.

关键词： Adders cmos technology Energy consumption Topology Voltage Frequency cmos logic circuits Added delay Capacitance Portable computers

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Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing

Comparing the robustness of fault-tolerant enhancements when...

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International Conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Yocheved Dotan Orgad Chen Gil Katz Dept. of Electrical and Computer Eng. Ruppin Academic Center Ruppin Israel

New challenges are arising in the design of computer systems with the emergence of new nanometer-scale devices and sophisticated fabrication techniques. Unfortunately, the yield, reliability, and drive characteristics of these new deep-submicron and nano-scale devices are different from the corresponding characteristics of conventional cmos devices. It is expected that future circuit technologies will have substantially higher defect densities and dynamic fault rates. There is no consensus yet on which technology will be selected and which of the traditional logic designs has an advantage for fault tolerant nano-computing. In this work, we compare the robustness of several fault-tolerant approaches applied to lookup table design and random logic design for a wide range of fault rates. Implementing fault tolerance in a circuit using TMR and Hamming and Hsiao error correcting codes with a lookup table design style gives better fault coverage compared with a random gate design style. TMR is the best fault-tolerance technique when implemented using the lookup table design. However, TMR was the worst technique for fault rates greater than 0.5% when implemented using random logic design and no gate level is fault free.

关键词： Robustness Fault tolerance Table lookup Circuit faults logic design Nanoscale devices cmos technology cmos logic circuits logic devices Fabrication

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Dynamic forward body bias enhanced tri-mode MTcmos

Dynamic forward body bias enhanced tri-mode MTCMOS

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： Hailong Jiao Volkan Kursun Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Hong Kong China

Ground bouncing noise produced during reactivation events is an exacerbating challenge to maintain accurate logic levels in Multi-threshold cmos (MTcmos) circuits. A new noise-aware MTcmos circuit with dynamic forward body bias is explored in this paper to minimize the ground bouncing noise with smaller sleep transistors. The dynamic-forward-body-biased MTcmos circuit lowers the peak ground bouncing noise by up to 27.76% while reducing the size of the additional sleep transistor by 85.71% as compared to the previously published noise-aware MTcmos techniques with standard zero-body-biased high threshold voltage sleep transistors. Furthermore, the proposed forward body bias circuit technique achieves up to 14.67% noise reduction and 70% sleep transistor downsizing as compared to a previously published forward-body-biased tri-mode MTcmos circuit technique. The design tradeoffs between ground bouncing noise and leakage power consumption are evaluated for various MTcmos circuits in a UMC 80 nm cmos technology.

关键词： Circuit noise Threshold voltage Energy consumption Active noise reduction Integrated circuit noise cmos technology cmos logic circuits Noise reduction Subthreshold current Active circuits

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Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic cmos Process

Demonstration of Conductive Bridging Random Access Memory (C...

引用

IEEE International Memory Workshop (IMW)

作者： Chakravarthy Gopalan Yi Ma Tony Gallo Janet Wang Ed Runnion Juan Saenz Foroozan Koushan Shane Hollmer Adesto Technologies Sunnyvale CA USA

ISBN: (纸本)9781424467198;9781424467211

Today's main stream NVM technologies require operational conditions that are incompatible with modern low voltage logic cmos designs. This characteristic results in complex integration issues as well as costly process and array concept especially for embedded NVM use models. Conductive bridging memory cell (CBRAM) technology is an attractive emerging memory technology that offers simple integration and scalable operational conditions. These unique features make CBRAM technology an ideal candidate for embedded applications. In this paper, we have shown successful integration of CBRAM into Copper and Aluminum back end logic cmos processes with minimal number of added masks.

关键词： Random access memory cmos logic circuits cmos process cmos technology Nonvolatile memory Low voltage logic design Semiconductor device modeling Copper Aluminum

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Ternary multiplier of multigate single electron transistor: Design using 3-T gate

Ternary multiplier of multigate single electron transistor: ...

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International Conference on Control and Automation (ICCA)

作者： Gang Wu Li Cai Sciences Institute Air Force Engineering University China

Due to the single electron transistor has the characteristics coulomb oscillation and adjustable threshold voltage, the single electron transistor is adapted to design the multiple value circuit. In this paper, a ternary multiplier is designed based on multigate single electron transistor, and the design uses the 3-T gate. The designed circuits have been simulated by SPICE. The results of simulation indicate the proposed ternary multiplier circuit has the excellence of simpler structure, smaller signal delay and lower power.

关键词： Single electron transistors cmos technology Algebra logic circuits Threshold voltage Circuit simulation Integrated circuit technology cmos logic circuits Computational modeling logic gates

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Applications of C-AFM analysis techniques at advanced IC on SRAM soft failure

Applications of C-AFM analysis techniques at advanced IC on ...

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International Symposium on Physical & Failure Analysis of Integrated circuits

作者： Hong Bo Zhang Wilson Lee Cheng Hoe Ren De Lin Wai Tuck Leong United Microelectronics Corporation Limited Singapore

ISBN: (纸本)9781424455966;9781424455980

The application of the conductive atomic force microscope (C-AFM) has been widely reported as a useful method of failure analysis in semiconductor field of nanometer scale science and technology, Especially for hard failure and soft failure identification and localization at logic and SRAM in cmos process. This paper will demonstrate a new application of the C-AFM to identify the electric characteristic of SRAM soft failure in cmos process. After taking electrical measurement, plain view SEM and cross-section TEM will reveal and understand the physical root cause of the electrical failure. After that, the principle of application for C-AFM on this SRAM soft failure analysis will be discussed.

关键词： Failure analysis Application specific integrated circuits Random access memory Atomic force microscopy Scanning electron microscopy cmos process Transmission electron microscopy cmos technology cmos logic circuits Electric variables

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