检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,880 篇 会议
644 篇 期刊文献
3 篇 学位论文

馆藏范围

4,527 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,168 篇 工学
- 821 篇 电气工程
- 351 篇 电子科学与技术（可...
- 247 篇 计算机科学与技术...
- 51 篇 材料科学与工程（可...
- 51 篇 控制科学与工程
- 50 篇 核科学与技术
- 36 篇 信息与通信工程
- 30 篇 软件工程
- 25 篇 机械工程
- 24 篇 仪器科学与技术
- 4 篇 生物医学工程（可授...
- 3 篇 光学工程
- 1 篇 力学（可授工学、理...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 交通运输工程
- 1 篇 网络空间安全
100 篇 理学
- 77 篇 物理学
- 18 篇 系统科学
- 6 篇 化学
- 1 篇 生物学
27 篇 管理学
- 27 篇 管理科学与工程(可...
5 篇 医学
- 4 篇 临床医学
- 1 篇 基础医学(可授医学...
- 1 篇 特种医学
3 篇 教育学
- 3 篇 教育学
1 篇 文学
- 1 篇 新闻传播学
1 篇 艺术学
- 1 篇 设计学（可授艺术学...

主题

4,527 篇 cmos logic circu...
1,837 篇 cmos technology
997 篇 logic circuits
899 篇 logic design
782 篇 clocks
773 篇 voltage
721 篇 logic devices
640 篇 logic gates
633 篇 cmos process
609 篇 energy consumpti...
518 篇 circuit simulati...
504 篇 delay
500 篇 very large scale...
499 篇 circuit testing
447 篇 switches
420 篇 semiconductor de...
410 篇 power dissipatio...
365 篇 threshold voltag...
361 篇 logic testing
339 篇 mosfets

机构

48 篇 ibm thomas j. wa...
25 篇 faculty of infor...
22 篇 texas instrument...
21 篇 department of el...
17 篇 central research...
17 篇 department of el...
16 篇 philips research...
16 篇 department of el...
15 篇 department of in...
14 篇 school of electr...
14 篇 intel corporatio...
14 篇 infineon technol...
13 篇 department of el...
13 篇 massachusetts in...
12 篇 lsi logic corpor...
12 篇 department of el...
12 篇 department of el...
10 篇 intel corporatio...
10 篇 semiconductor de...
10 篇 imec leuven

作者

37 篇 k. roy
25 篇 jianping hu
18 篇 m. hashizume
18 篇 m.i. elmasry
17 篇 y. berg
16 篇 j.b. kuo
16 篇 t. tamesada
15 篇 c. sechen
13 篇 d. al-khalili
13 篇 k.w. current
13 篇 s. vassiliadis
12 篇 kuo-hsing cheng
12 篇 sung-mo kang
12 篇 m. shams
12 篇 yusuf leblebici
11 篇 a. afzali-kusha
11 篇 f. matsuoka
11 篇 n.k. jha
11 篇 e.j. mccluskey
11 篇 j. figueras

语言

4,435 篇 英文
51 篇 其他
41 篇 中文

检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是281-290 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Crosstalk analysis in Carbon Nanotube interconnects and its impact on gate oxide reliability

Crosstalk analysis in Carbon Nanotube interconnects and its ...

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： Debaprasad Das Hafizur Rahaman School of VLSI Technology Bengal Engineering and Science University Shibpur India

The work analyses the crosstalk effects in Carbon Nanotube (CNT), and its impact on the gate oxide reliability. Using the existing models of CNT, the circuit parameters for CNT-bundle interconnect are calculated and the equivalent circuit has been developed to perform the crosstalk analysis. The crosstalk induced overshoot/undershoots have been estimated and the impact of the overshoot/undershoots on the gate oxide reliability in terms of failure-in-time (FIT) rate is calculated. A similar analysis is performed for Cu interconnects and comparisons are made with CNT based interconnect results. It has been found that the CNT based interconnect is more suitable in VLSI circuits as far as the gate oxide reliability is concerned.

关键词： Crosstalk Carbon nanotubes Integrated circuit interconnections cmos logic circuits Voltage Very large scale integration cmos technology Equivalent circuits Performance analysis Delay

来源：评论

学校读者我要写书评

暂无评论

Electrical characterization of contact level PVC (Passive Voltage Contrast) test using a nanoprober

Electrical characterization of contact level PVC (Passive Vo...

引用

International Symposium on Physical & Failure Analysis of Integrated circuits

作者： Sang-Cheol Han Seong-Jun Cho Jeong-Un Choi Jeong-Uk Han Sang-Rok Hah Semiconductor Business System LSI Division Process Integration Group Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)9781424455966;9781424455980

PVC (Passive Voltage Contrast) fault isolation method by using a SEM (Scanning Electron Microscope) has been widely used for isolating the defective mc (metal contact) in the cmos logic SRAM bit cell array. The low power (LP) processed sram cells are easy to charging under PVC test and it helps isolating defective contacts in the cell. However, some device such as a high speed (HS) sram cell is hard to charging in PVC test by unknown reason. It makes difficulties for isolating defective contacts in the sram cell array. In this paper, our group analyzed the electrical current of each contact in sram cell using a nanoprobing technique and correlated it with PVC charged contact images, respectively. Also, the difference of PVC charging status between LP and HS SRAM are characterized electrically by using a nanoprober. The nanoprobing result indicates that a slight increasing a leakage current of about 10pA can abruptly change the charging brightness from dark to grey. Finally, we can found some clues for making grey contacts of HS SRAM using not only a nanoprobing but also a HRTEM (High Resolution Transmission Electron Microscope) image.

关键词： Contacts Voltage Testing Scanning electron microscopy Random access memory logic arrays Log periodic antennas cmos logic circuits logic devices Image analysis

来源：评论

学校读者我要写书评

暂无评论

Novel circuit technique for reduction of active drain current in series/parallel PMOS transistors stack

Novel circuit technique for reduction of active drain curren...

引用

International Conference on Electronic Devices, Systems and Applications (ICEDSA)

作者： Vaibhav Neema Shailesh Singh Chouhan Sanjiv Tokekar IET Devi Ahilya University Indore India

ISBN: (纸本)9781424466290

Stacking of MOS transistors is used for minimization of standby current in Nano-scale cmos circuits. Stacking of PMOS is preferred over NMOS because value of active drain current in PMOS is less than NMOS. It results because of mobility of holes in PMOS is less than mobility of electrons in NMOS. In this paper we observed active drain current consumption by series/parallel combination of two and three PMOS transistors. This observation leads to propose the novel technique for reduction of active drain current in series/parallel PMOS assembly. The effect of V GS , V DS , V SB and intermediates node voltages is also addressed. The proposed circuit is simulated for TSMC 0.18 μm technology using Spice© simulator.

关键词： MOSFETs Power dissipation cmos logic circuits Stacking MOS devices Circuit simulation Dynamic voltage scaling Very large scale integration logic circuits Capacitance

来源：评论

学校读者我要写书评

暂无评论

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm cmos

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC i...

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： Pieter Harpe Cui Zhou Xiaoyan Wang Guido Dolmans Harmke de Groot Holst Centre-IMEC Eindhoven Netherlands

An 8 b SAR ADC is presented. The 90 nm cmos prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic cmos logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.

关键词： Sampling methods Clocks Energy consumption cmos logic circuits Frequency measurement Parasitic capacitance Power measurement Switched capacitor networks Switches Inverters

来源：评论

学校读者我要写书评

暂无评论

A Novel Signed Array Multiplier

A Novel Signed Array Multiplier

引用

International Conference on Advances in Computer Engineering (ACE)

作者： Debaprasad Das Hafizur Rahaman School of VLSI Technology Bengal Engineering and Science University Shibpur India

ISBN: (纸本)9781424471546;9780769540580

A new architecture for the signed binary multiplier is presented in this paper. The proposed signed array multiplier has 54% area overhead as compared to Baugh Wooley multiplier but is 25% faster than the previous designs. The new design works with the operands in two's complement format. The multiplier is based on a basic 2 × 2 multiplier. The final product is adjusted for negative operands. The design is implemented in TSMC 0.18 um process technology node and TSPICE is used for design and simulation.

关键词： Very large scale integration Computer architecture Signal processing algorithms cmos logic circuits Adders Design methodology logic design Digital arithmetic Digital signal processing Registers

来源：评论

学校读者我要写书评

暂无评论

Analytical model for TDDB-based performance degradation in combinational logic 10

Analytical model for TDDB-based performance degradation in c...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Mihir Choudhury Vikas Chandra Kartik Mohanram Robert Aitken Department of Electrical and Computer Engineering Rice University Houston USA ARM Research and Development San Jose USA

ISBN: (纸本)9783981080162

With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred to as time-dependent dielectric breakdown (TDDB), is emerging as one of the most important sources of performance degradation in nanoscale cmos devices. This paper describes an accurate analytical model to predict the delay of combinational logic gates subject to TDDB. The analytical model can be seamlessly integrated into a static timing analysis tool to analyze TDDB effects in large combinational logic circuits across a range of supply voltages and severity of oxide breakdown. Simulation results for an early version of an industrial 32 nm library show that the model is accurate to within 3% of SPICE with orders of magnitude improvement in runtime.

关键词： Analytical models Degradation cmos logic circuits logic devices Dielectric breakdown Breakdown voltage Lead compounds Electric breakdown Nanoscale devices Delay

来源：评论

学校读者我要写书评

暂无评论

A 76GHz PLL for mm-wave imaging applications

A 76GHz PLL for mm-wave imaging applications

引用

Microwave, MTT-S International Symposium

作者： Khoa M. Nguyen Helen Kim Charles G. Sodini Massachusetts Institute of Technology Cambridge MA USA Lincoln Laboratory Lexington MA USA

A 76 GHz phase-locked loop (PLL) was designed in 0.13 μm IBM Bicmos8HP technology with the intended application of millimeter-wave imaging. The PLL has a type II second order loop filter. The voltage-controlled oscillator (VCO) uses a cross-coupled BJT topology with capacitor feedback. The divider chain has nine divide-by-2 static frequency dividers in which the first seven use ECL logic and are followed by two cmos stages. Measurement results show a de-embedded single-ended output power of -2 dBm, a phase noise of -81 dBc/Hz at 1 MHz offset from the carrier, and a total power dissipation of 107 mW.

关键词： Phase locked loops Voltage-controlled oscillators Millimeter wave measurements Millimeter wave technology Filters Topology Capacitors Feedback Frequency conversion cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

All digital ADC with linearity correction and temperature compensation

All digital ADC with linearity correction and temperature co...

引用

IEEE Instrumentation and Measurement Technology Conference

作者： Marcelo Negreiros Luigi Carro Gustavo Cassel UFRGS Instituto de Informática Porto Alegre Brazil CEEE Porto Alegre Brazil

While digital circuits benefit from high-density digital cmos technology, the design of analog and mixed signal blocks in the same technology is a higher challenge at each new technology node. AD converters are an example of such blocks. A possible solution is the implementation of ADCs in digital technology using logic gates as a voltage controlled oscillator. However, the limited linearity and temperature sensitivity are known issues. In this paper, a linearity correction technique that is also able to compensate for temperature effects is used. Results indicate the feasibility of the approach.

关键词： Linearity cmos technology Temperature sensors Digital circuits cmos digital integrated circuits cmos analog integrated circuits Signal design logic gates cmos logic circuits Voltage-controlled oscillators

来源：评论

学校读者我要写书评

暂无评论

Single phase MOS-NDR mobile networks

Single phase MOS-NDR mobile networks

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Juan Nuñez María J. Avedillo José M. Quintana Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica Consejo Superior de Investigaciones Científicas CSIC Universidad de Sevilla Seville Spain Instituto de Microelectrónica de Sevilla Consejo Superior de Investigaciones Cientificas (CSIC) and Universidad de Sevilla Américo Vespucio s/n Sevilla SPAIN

Devices with an I-V characteristic exhibiting Negative Differential Resistance (NDR) are attractive from the circuit design point of view as it has been demonstrated by Resonant Tunneling Diodes (RTDs) circuits. Ideas coming from RTD-based designs can be exported to an “all cmos” environment by using transistor circuits to generate the NDR characteristic (MOS-NDR). In this paper novel programmable MOS-NDRs are proposed and used to realize threshold logic gates on the basis of the MOnostable to BIstable Operating principle. It is shown that these gates can be connected to build up networks that are operated in a pipelined fashion using a single phase clock scheme.

关键词： cmos logic circuits Clocks logic devices logic circuits Circuit synthesis Resonant tunneling devices Diodes RLC circuits Character generation logic gates

来源：评论

学校读者我要写书评

暂无评论

A novel 4∶2 compressor for high speed and low power applications

A novel 4∶2 compressor for high speed and low power applica...

引用

Iranian Conference on Electrical Engineering (ICEE)

作者： Shirin Pourashraf Masoud Sayedi ECE Department Isfahan University of Technology Isfahan Iran

ISBN: (纸本)9781424467600

In this paper, we present a novel logic 4:2 compressor which uses the Pass-transistor and domino logic structures. The design is simulated using HSPICE in a 1.8-v 0.18-μm cmos technology. Power dissipation, delay and maximum frequency are measured. Simulation results show that the proposed design has lower delay and power consumption compared with some previously reported designs.

关键词： cmos technology cmos logic circuits Energy consumption Delay Adders Power dissipation logic devices Digital signal processing Frequency Power measurement

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共453页 << < 25 26 27 28 29 30 31 32 33 34 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：