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检索条件"主题词=CMOS Logic Circuits"

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Behavioral model for high-speed digital buffer/driver

Behavioral model for high-speed digital buffer/driver

引用

International Workshop on Integrated Nonlinear Microwave and Millimeterwave circuits, INMMIC

作者： W. Dghais T. R. Cunha J. C. Pedro Instituto de Telecomunicações Universidade de Aveiro Aveiro Portugal

This paper presents a new behavioral macromodeling approach for high-speed digital output buffers/drivers. Unlike traditional behavioral black-box modeling techniques, our approach consists of modeling digital drivers based on their physical constitution in order to simplify the complexity of the nonlinear parametric relationship and include the package network within the nonlinear model structure. For that, the operation of the driver was analyzed by dividing the problem into a nonlinear static and a linear dynamic part. The resulting model is useful for the signal integrity (SI) analysis and has a good performance in terms of both accuracy and speed.

关键词： Packaging Semiconductor device modeling Driver circuits cmos logic circuits Capacitance Integrated circuit interconnections Timing Bonding Wire Inductance

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Peak current reduction using an MTcmos technique

Peak current reduction using an MTCMOS technique

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： Liang-Ying Lu Tsung-Yi Wu Lih-Yih Chiou Jing-Wen Shi Department of Electrical Engineering National Cheng Kung University Taiwan Department of Electronic Engineering National Changhua University of Education Taiwan

In a digital circuit system, IR drop effect can be alleviated by reducing the peak current of the system. Clock skew scheduling is a popular technique for peak current reduction. In this paper, we propose two algorithms that apply a Multiple Threshold cmos (MTcmos) technique rather than clock skew scheduling to do peak current reduction. MTcmos techniques are feasible to reduce peak current because different threshold cells have different cell delays and current waveforms. Experimental results show that our technique can reduce the peak current up to 47.7%. Our proposed technique can reduce not only peak current but also leakage current. Moreover, a peak current reduction algorithm using a clock skew technique or an opposite-phase clock scheme can employ our proposed technique to further reduce the peak current of a circuit.

关键词： Clocks Flip-flops Voltage Leakage current Delay cmos technology logic gates cmos logic circuits logic circuits Electronic design automation and methodology

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QCA circuit design based on novel optimal ULG.2

QCA circuit design based on novel optimal ULG.2

引用

International Conference on Industrial Mechatronics and Automation, ICIMA

作者： Linrong Xiao Shiyan Ying Taiyi Pei Department of Electronic Engineering Jiaxing University Jiaxing China College of Information Engineering Zhejiang University of Science and Technology Hangzhou China

ISBN: (纸本)9781424476534

Quantum-dot cellular automata (QCA) is a promising nanotechnology, with the potential for faster speed, smaller size and lower power consumption than cmos technology. In QCA circuit design, However, wire-crossing is an issue. Universal logic gates (ULG) have stronger function than traditional logic gates. This paper begins with a review of QCA. Then a novel QCA optimal ULG.2 is obtained using a new algorithm and modular design methodology. Some circuits are implemented with the ULG.2. As an example, finally, a full adder/subtraction is constructed by applying the ULG.2. The simulation results confirm that all the proposed circuits not only hold correct logic function but also achieve a considerable wire-crossing count reduction in comparison to the other previous designs.

关键词： Quantum cellular automata Circuit synthesis cmos technology logic gates cmos logic circuits Quantum dots Nanotechnology Energy consumption Design methodology Adders

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Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications 10

Regular fabric design with ambipolar CNTFETs for FPGA and st...

引用

IEEE International Symposium on Nanoscale Architectures (NANOARCH)

作者： Michele De Marchi M. Haykel Ben Jamaa Giovanni De Micheli EPF Lausanne Lausanne Switzerland CEA-LETI/MINATEC Grenoble France

ISBN: (纸本)9781424480180

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we selected a number of gates with an And-Or-Inverter structure and produced a first comparison with existent medium-grained logic blocks, like the Actel ACT1 and 4-input LUTs. Preliminary evaluation of our gates indicates improvements of around 47% over the ACT1 and of about 18× with respect to 4-input LUTs in terms of area×normalized delay.

关键词： Fabrics Field programmable gate arrays Application specific integrated circuits logic design cmos logic circuits logic gates Table lookup Delay cmos technology logic devices

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A complementary single-electron 4-bit multiplexer

A complementary single-electron 4-bit multiplexer

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： T. Tsiolakis N. Konofaos G. Ph. Alexiou Department of Computer Engineering & Informatics University of Patras Patras Greece Department of Information & Communications Systems Engineering University of Aegean Samos Greece

The design and simulation of a single-electron 4-1 complementary multiplexer is being presented using two Monte Carlo based tools. Both the behavior and the stability of the circuit were verified while its free energy and its speed were also examined and analyzed. The results confirmed that the circuit behaved as a complementary multiplexer. Moreover, the currents through the circuit were examined under the operating temperature, while a stable operation of the circuit was verified without any noise present at the output points.

关键词： Multiplexing Electrons Voltage Circuit simulation Temperature Tunneling cmos technology cmos logic circuits Capacitance Design engineering

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Carbon nanotube circuits: Living with imperfections and variations 10

Carbon nanotube circuits: Living with imperfections and vari...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Jie Zhang Nishant Patil Albert Lin H. -S. Philip Wong Subhasish Mitra Department of Electrical Engineering University of Stanford Stanford CA USA Department of Computer Science University of Stanford Stanford CA USA

ISBN: (纸本)9783981080162

Carbon Nanotube Field-Effect Transistors (CNFETs) can potentially provide significant energy-delay-product benefits compared to silicon cmos. However, CNFET circuits are subject to several sources of imperfections. These imperfections lead to incorrect logic functionality and substantial circuit performance variations. Processing techniques alone are inadequate to overcome the challenges resulting from these imperfections. An imperfection-immune design methodology is required. We present an overview of imperfection-immune design techniques to overcome two major sources of CNFET imperfections: metallic Carbon Nanotubes (CNTs) and CNT density variations.

关键词： Carbon nanotubes Silicon Semiconductivity CNTFETs logic circuits Substrates cmos technology Computer science cmos logic circuits Circuit optimization

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Basic cell of a reconfigurable antenna with dual polarization for WIMAX applications

Basic cell of a reconfigurable antenna with dual polarizatio...

引用

European Conference on Antennas and Propagation, EuCAP

作者： José Luis Masa-Campos Víctor Luzón-Mesas Ramiro José López-Colino Grupo de Sistemas de Radiocomunicaciones y Comunicaciones Ópticas (GSRCO) Universidad Autónoma de Madrid Madrid Spain

A 8 × 8 reconfigurable array antenna with dual lineal/circular polarization for WIMAX applications at 3.5 GHz has been designed. The antenna is composed of 4 elements basic cell sub-arrays with a Butler matrix inside. The basic cell sub-arrays are combined by means of digital phase shifters. The measured results of the radiating elements and RF modules are presented.

关键词： Polarization WiMAX Butler matrix Switches Radio frequency Phase shifters Antenna measurements Switching circuits cmos logic circuits Transceivers

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Novel ultra low voltage transconductance amplifier

Novel ultra low voltage transconductance amplifier

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Y. Berg Department of Informatics University of Oslo Oslo Norway

In this paper we explore symmetric floating-gate cmos circuits aimed for ultra-low analog design. The analog transconductance amplifier presented may operate down to 250mV in a STM 90nm cmos process with an inherent threshold voltage of 270mV. The ultra-low transconductance amplifier has a current boost function and resembles switch-cap and auto-zero circuits. The current boost technique have been used to implement ultra-low voltage digital logic. Simulated data for a ST 90nm cmos process, using the the Cadence design tool, are included.

关键词： Low voltage Transconductance cmos technology cmos process Threshold voltage MOSFETs Clocks Analog circuits cmos analog integrated circuits cmos logic circuits

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Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix

Level matrix propagation for reliability analysis of nano-sc...

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IEEE International Symposium on Quality Electronic Design

作者： Hicham Ezzat Lírida Naviner Université Française d''Egypte Cairo Egypt Télécom ParisTech CNRS-LTCI Institut TELECOM Paris France

ISBN: (纸本)9781424464548

As cmos technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.

关键词： Circuit analysis cmos technology Integrated circuit reliability logic circuits Integrated circuit technology Scalability logic gates Circuit faults Telecommunications cmos logic circuits

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Analog to digital converters for high temperature applications: The modeling approach issue

Analog to digital converters for high temperature applicatio...

引用

IEEE Instrumentation and Measurement Technology Conference

作者： Sahbi Baccar Saeed Mian Qaisar Dominique Dallet Timothée Lévi Vladimir Shitikov François Barbara Laboratory IMS-ENSEIRB CNRS Talence Cedex France Schlumberger Clamart Cedex France

ISBN: (纸本)9781424428328;9781424428335

The analog to digital converter (ADC) is an essential part of measurement, communications and processing systems. ADC modeling is a rich trend in the ADC research areas. High temperature applications have witnessed a real growth in last years. The motivation of this article is to describe an appropriate choice of the ADC modeling approach for high temperature ranges. The context of high temperature electronics systems is briefly described here and allows us to understand the challenges of such modeling. Comparing most known techniques enables us to make a suitable modeling choice for high temperature. An appropriate method for modeling was presented.

关键词： Analog-digital conversion Temperature distribution Consumer electronics Temperature sensors cmos technology Aerospace electronics cmos logic circuits Internal combustion engines Aerospace industry Instruments

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