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检索条件"主题词=CMOS Logic Circuits"

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Comparing crossbar-based nano/cmos architectures

Comparing crossbar-based nano/CMOS architectures

引用

International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Ciprian Teodorov CNRS UMR 3192 Laboratory-STICC ISSTB Université de Brest Brest France Université Européenne de Bretagne France

ISBN: (纸本)9781424463381;9781424463404

During the last few years, a novel set of nanoscale technologies has emerged as an alternative to traditional cmos circuits. They bring certain promises such as high-density, reduced manufacturing costs, but they also present some challenges. Trying to compare some of the proposed architectures we realized that it is impossible to objectively evaluate them, problem that hinder our ability to practically develop these architectures. To compare these architectures we extracted the similarities between these fabrics and based on these similarities we tried to match the results presented in the literature. Following this methodology we were unable to objectively compare these emergent architectures. In this paper we present the main reasons why such an evaluation is not practical and we show how a common vocabulary and design methodology can solve this problem.

关键词： Computer architecture cmos logic circuits Diodes Reconfigurable logic Fabrics cmos technology Integrated circuit interconnections Reconfigurable architectures Field programmable gate arrays Pulse inverters

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Dual-stylus-arm scratch drive micro-robots controlled by a communication channel

Dual-stylus-arm scratch drive micro-robots controlled by a c...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Jung H. Cho Mark G. Arnold Lehigh University Bethlehem PA USA

A novel approach to controlling the mobility of MEMS SDA Scratch-Drive-Actuator (SDA) micro-robots is presented. The operation of MEMS SDA has been well demonstrated by the research of Donald et al.. An improvement of adding an additional stylus arm to control left and right rotation as well as using both arms to halt was presented in. In order to eliminate the complication of different stress curling to control multiple micro-robots, an alternative solution of controlling electrical connection between parallel plate body and stylus arms is presented. A Universal Asynchronous Receiver Transmitter (UART) was developed and applied which allowed a micro-robot to move towards a target using global communication channel to guide the robot's path.

关键词： Communication system control Communication channels Voltage Micromechanical devices Robots Arm Electrodes cmos logic circuits Stress control Optical transmitters

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Intel LVS logic as a combinational logic paradigm in CNT technology 10

Intel LVS logic as a combinational logic paradigm in CNT tec...

引用

IEEE International Symposium on Nanoscale Architectures (NANOARCH)

作者： Bao Liu Zhen Cao Jun Tao Xuan Zeng Pushan Tang Philip H.-S. Wong ECE Department University of Technology San Antonio TX USA EE Department Fudan University Shanghai China University of Stanford Stanford CA USA

ISBN: (纸本)9781424480180

In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare cmos static logic, transmission gate logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that cmos static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while transmission gate logic and Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with cmos static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.

关键词： cmos logic circuits cmos technology logic gates Predictive models Energy consumption Combinational circuits Silicon Semiconductor device modeling Power system modeling SPICE

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Spintronic memristor devices and application 10

Spintronic memristor devices and application

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Xiaobin Wang Yiran Chen Seagate Technologies Inc. Bloomington MN USA

ISBN: (纸本)9783981080162

Spintronic memristor devices based upon spin torque induced magnetization motion are presented and potential application examples are given. The structure and material of these proposed spin torque memristors are based upon existing (and/or commercialized) magnetic devices and can be easily integrated on top of a cmos. This provides better controllability and flexibility to realize the promises of nanoscale memristors. Utilizing its unique device behavior, the paper explores spintronic memristor potential applications in multibit data storage and logic, novel sensing scheme, power management and information security.

关键词： Magnetoelectronics Memristors Torque Magnetic materials Magnetization Commercialization Magnetic devices Controllability Memory cmos logic circuits

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Zero-cost MTP high density NVM modules in a cmos process flow

Zero-cost MTP high density NVM modules in a CMOS process flo...

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IEEE International Memory Workshop (IMW)

作者： A. Atrash G. Cassuto W. Chen V. Dayan O. Galzur M. Gutman A. Heiman G. Hunsinger D. Nahmad A. Parag E. Pikhay Y. Roizin B. Smith A. Strum T. Tishbi R. Teggatz Triune Systems Richardson TX USA TowerJazz Limited Migdal HaEmek Israel

ISBN: (纸本)9781424467198

A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64 bit to 64 kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18 μm cmos process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10 k program/erase cycles and 10 year data retention at 150°C is demonstrated.

关键词： cmos process Nonvolatile memory cmos technology Voltage Energy management Costs MOSFETs Mass production cmos logic circuits logic devices

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Optimum leakage dynamic array design

Optimum leakage dynamic array design

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International Symposium on VLSI Design, Automation and Test

作者： Maciej Bajkowski Giao Pham Murali Vepadharmalingam Ultra Mobility Group Intel Corporation Limited USA

ISBN: (纸本)9781424452699;9781424452712

In recent microprocessor designs Register File (RF) and Read Only Memory (ROM) arrays comprise over 50% of the total core area. These arrays account for a significant portion of the total leakage power. We propose two novel design techniques: Tri-state Domino Circuit (TDC) and Selective Pre-Charge (SPC). We combine these techniques to maximize leakage savings without affecting downstream logic by using a new noise robust state preserving Set Dominant Latch (SDL). Our simulation results, in 32nm cmos technology, demonstrate that we are able to reduce the read path leakage power for a 256 entry 1 rlw RF by 81%.

关键词： Radio frequency Read only memory cmos technology Microprocessors Registers cmos logic circuits Circuit noise Noise robustness Latches Circuit simulation

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FPGA based on integration of memristors and cmos devices

FPGA based on integration of memristors and CMOS devices

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Wei Wang Tom T. Jing Brian Butcher College of Nanoscale Science and Engineering State University of New York Albany NY USA

This paper introduces a novel cmos-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based cmos-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a cmos-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel cmos-memristor routing switches are developed to replace the cmos routing switches to achieve significant density enhancement and power reduction. The simulation results demonstrate that 2D and 3D mFPGAs provide at least a 2X to 3X overall improvement in terms of area reduction, and a 20% lower power consumption, compared with corresponding cmos FPGA architectures.

关键词： Field programmable gate arrays Memristors Switches cmos logic circuits Routing Energy consumption Nanoscale devices Reconfigurable architectures Circuit simulation Buildings

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Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization

Defect-aware nanocrossbar logic mapping using Bipartite Subg...

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IEEE European Test Symposium (ETS)

作者： Sezer Gören H. Fatih Ugurdag Okan Palaz Department of Computer Engineering Bahçesehir University Istanbul Turkey Dept. of Computer Engineering Bahcesçhir University Istanbul Turkey

ISBN: (纸本)9781424458349;9781424458332;9781424458356

This paper addresses the NP-complete problem of mapping a logic function on to a nanocrossbar with a known defect map. We first show that this problem can be transformed into a Bipartite SubGraph Isomorphism (BSGI) problem. Then we present our proposed KNS-2DS algorithm, which canonizes both graphs in N 2 time (N being the number of nodes) and then matches them in N 3 time in the worst case. KNS-2DS uses a K-Neighbor Sort (KNS) to initialize our main contribution 2D-Sort (2DS). 2DS is an iterative rough canonizer that lets a straightforward matching algorithm complete the job. Our algorithm offers very short run-times (due to canonization) compared to previous work and has success on all benchmarks. KNS-2DS is also novel from the perspective of the BSGI problem in the sense that it is based on canonization but not on a search tree with backtracking.

关键词： cmos logic circuits Programmable logic arrays Iterative algorithms logic functions Runtime NP-complete problem Reconfigurable architectures Reconfigurable logic Nanowires Diodes

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Memristor based programmable threshold logic array 10

Memristor based programmable threshold logic array

引用

IEEE International Symposium on Nanoscale Architectures (NANOARCH)

作者： Jeyavijayan Rajendran Harika Manem Ramesh Karri Garrett S. Rose Department of Electrical and Computer Engineering Polytechnic Institute New York University Brooklyn NY USA

ISBN: (纸本)9781424480180

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

关键词： Programmable logic arrays Memristors cmos logic circuits logic devices Boolean functions logic design Resistors Voltage logic circuits Delay

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Delay Insensitivity Does Not Mean Slope Insensitivity!

Delay Insensitivity Does Not Mean Slope Insensitivity!

引用

International Symposium on Advanced Research in Asynchronous circuits and Systems

作者： Florent Ouchet Katell Morin-Allory Laurent Fesquet TIMA Laboratory Grenoble INP UJF CNRS France

Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes in details this phenomenon and studies the robustness of different C-element topologies. The simulations, which have been performed in 130, 65 and 45 nm cmos technologies, show an overview of the C-element behavior in presence of these slow ramps. This gives a comprehensive understanding of the phenomenon and suggests an appropriate approach for choosing the well-suited C-element topology for everybody facing these difficulties.

关键词： Circuit simulation cmos technology Asynchronous circuits Robustness Voltage Circuit topology Aging cmos logic circuits Delay systems Laboratories

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