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检索条件"主题词=CMOS Logic Circuits"

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A toggle-type peak hold circuit for local power supply noise detection

A toggle-type peak hold circuit for local power supply noise...

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： Yuki Tamaki Toru Nakura Makoto Ikeda Kunihiro Asada Department of Electronic Engineering and Information Systems University of Tokyo Bunkyo Tokyo Japan VLSI Design and Education Center University of Tokyo Bunkyo Tokyo Japan Tokyo Daigaku Bunkyo-ku Tokyo JP

In this paper, a new peak hold circuit which detects the top value and the bottom value of the power supply noise of a VLSI circuit is proposed. We can make a noise map by distributing the circuit over the chip and find hot-spots in which large power supply noise occurs. This circuit needs no extra clean power supply or external clock signal. Also, low power consumption can be expected because it is composed simple and small. Our circuit can hold both the top peak value and bottom peak value by changing only one gate logic. Moreover, our circuit has a mechanism of DC offset cancellation. This circuit has a resolution of 10mV at 100MHz. The output value from two or more circuits can be transmitted via a shared single wire. HSPICE simulation using a 0.18μm cmos process technology validates its operation.

关键词： Power supplies Circuit noise Very large scale integration Clocks Energy consumption logic gates cmos logic circuits logic circuits Signal resolution Wire

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Exploiting time resolution in nanometre cmos data converters

Exploiting time resolution in nanometre CMOS data converters

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Luis Hernandez Andreas Wiesbauer Carlos III Technical University of Madrid Leganes Spain Infineon Technologies Austria AG Villach Austria

The challenges of analog electronics in nanometer cmos have motivated the search for new data converter architectures. This paper is a in introductory survey of new options to implement data converters seizing the high speed digital logic featured by the newest technologies. Classical comparator based ADC's may replaced by ring oscillators or pulse width modulators which are then sampled by Time to Digital Converters (TDC), bridging analog design with custom digital design. Continuous time sigma delta modulators can be enhanced replacing the quantizer by some kind of voltage to time encoder and a high speed sampling digital device. The paper will be supported by some chip examples.

关键词： Pulse width modulation converters Digital modulation cmos logic circuits cmos technology Ring oscillators Pulse width modulation Analog-digital conversion Delta-sigma modulation Delta modulation Voltage

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Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits 10

Ultra-low power mixed-signal design platform using subthresh...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Armin Tajalli Yusuf Leblebici Microelectronic Systems Laboratory (LSM) Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9783981080162

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold source-coupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice.

关键词： Power dissipation cmos logic circuits Voltage Energy management Power system management Process design Circuit topology Design engineering Power engineering and energy Energy consumption

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Rule-based optimization of reversible circuits 10

Rule-based optimization of reversible circuits

引用

Asia and South Pacific Design Automation Conference

作者： Mona Arabzadeh Mehdi Saeedi Morteza Saheb Zamani Computer Engineering and IT Department Amirkabir University of Technology슠 Tehran Iran

ISBN: (纸本)9781605588377

Reversible logic has applications in various research areas including low-power design and quantum computation. In this paper, a rule-based optimization approach for reversible circuits is proposed which uses both negative and positive control Toffoli gates during the optimization. To this end, a set of rules for removing NOT gates and optimizing sub-circuits with common-target gates are proposed. To evaluate the proposed approach, the best-reported synthesized circuits and the results of a recent synthesis algorithm which uses both negative and positive controls are used. Our experiments reveal the potential of the proposed approach in optimizing synthesized circuits.

关键词： Circuit synthesis Quantum computing logic circuits cmos logic circuits Cost function logic design Boolean functions Design optimization Design engineering Application software

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A cmos temperature sensor with an energy-efficient zoom ADC and an Inaccuracy of ±0.25°C (3s) from −40°C to 125°C

A CMOS temperature sensor with an energy-efficient zoom ADC ...

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IEEE International Conference on Solid-State circuits (ISSCC)

作者： Kamran Souri Mahdi Kashmiri Kofi Makinwa Delft University of Technology Delft Netherlands

A 0.26 mm 2 cmos temperature sensor is realized in a 0.16 μm cmos process. It uses a hybrid SAR/ΔΣ (zoom) ADC to achieve 0.018°C resolution at 10S/s while dissipating 9 μW. After a 1-point trim, the sensor a... 详细信息

关键词： Temperature sensors Energy efficiency Capacitors cmos logic circuits Sampling methods Clocks Temperature measurement Energy resolution Voltage Micromechanical devices

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CNN implemented by nonlinear phase dynamics in nanoscale processes

CNN implemented by nonlinear phase dynamics in nanoscale pro...

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IEEE International Workshop on Cellular Nanoscale Networks and their Applications, (CNNA)

作者： Paul M. Riechers Richard A. Kiehl Department of Electrical and Computer Engineering University of California Los Angeles Davis CA USA

ISBN: (纸本)9781424466795;9781424466788

We discuss CNNs in which the states are defined by the electrical phase of a dynamic physical process, such as electron tunneling in ultra-small junctions or integrate-and-fire processes in nanoscale structures or molecules. Such processes produce impulsive "neuron-like" waveforms which can be coupled to nearest neighbors in a 1D, 2D, or 3D array. Input data can be represented by the distribution of dc bias level, initial charge, or coupling strength within the array. Information processing can be realized through the nonlinear dynamics produced by interactions between elements, which give rise to an evolution of complex patterns in the phase-state. In this paper, we discuss information processing for a model physical system based on Coulomb blockade in a 2D array of ultra-small tunnel junctions.

关键词： Cellular neural networks Tunneling Information processing logic circuits Electrons Nonlinear dynamical systems Oscillators logic gates Multivalued logic cmos logic circuits

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A CuxO-based resistive memory with low power and high reliability for SOC nonvolatile memory applications

A CuxO-based resistive memory with low power and high reliab...

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IEEE International Memory Workshop (IMW)

作者： M. Wang Y. L. Song H.J. Wan H.B. Lv P. Zhou T. A. Tang Y. Y. Lin R. Huang S. Song J. G. Wu H. M. Wu M. H. Chi ASIC and System State Key Laboratory Research Center of Semiconductor Memory and Application Fudan University Shanghai China SOC Technology Development Center Semiconductor Manufacturing International Corporation Shanghai China

ISBN: (纸本)9781424467198;9781424467211

A Cu x O-based resistive memory is successfully integrated in 0.13 μm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 μA. High thermal stability and small cell size less than 22 F 2 have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.

关键词： Nonvolatile memory Energy consumption cmos logic circuits logic devices Thermal stability Electrodes Tellurium logic testing Voltage Circuit testing

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Intel LVS logic in CNT technology

Intel LVS logic in CNT technology

引用

Midwest Symposium on circuits and Systems (MWSCAS)

作者： Xuan Zeng Bao Liu Zhen Cao Jun Tao Philip H.-S. Wong Pushan Tang Fudan University Shanghai China University of Stanford Stanford CA USA

In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare cmos static logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that cmos static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with cmos static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.

关键词： cmos logic circuits cmos technology Predictive models Energy consumption Combinational circuits Silicon Semiconductor device modeling Power system modeling SPICE logic functions

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Cascaded time difference amplifier using differential logic delay cell 10

Cascaded time difference amplifier using differential logic ...

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Asia and South Pacific Design Automation Conference

作者： Shingo Mandai Toru Nakura Makoto Ikeda Kunihiro Asada Department of Electrical Engineering and Information Systems University of Tokyo Japan VLSI Design and Education Center VDEC University of Tokyo Bunkyo Tokyo Japan

ISBN: (纸本)9781605588377

We introduce a 4 2 x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18¿m cmos process. By employing differential logic cells for the delay chain instead of cmos logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ±250ps input range.

关键词： Differential amplifiers Delay effects cmos logic circuits Switches Gain control Switching circuits Gain measurement Semiconductor device measurement cmos process Power supplies

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Multiobjective optimization for transistor sizing sub-threshold cmos logic standard cells

Multiobjective optimization for transistor sizing sub-thresh...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Matthias Blesken Sven Lütkemeier Ulrich Rückert System and Circuit Technology University of Paderborn Germany Cognitronic and Sensor Systems University of Bielefeld Germany

Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold cmos logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.

关键词： cmos logic circuits Power systems Robustness Energy consumption Propagation delay Design optimization Process design Algorithm design and analysis cmos process logic design

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