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International Conference on Electronic Computer Technology

作者： Jahanzeb Anwer Usman Khalid Narinderjit Singh Nor H. Hamid Vijanth S. Asirvadam Electrical & Electronics Engineering Department Universiti Teknologi Petronas Bandar Seri Iskandar Tronoh Perak Malaysia

Current trend of downscaling cmos transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in [1]. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of [1].

关键词： logic gates logic design Markov random fields Circuit noise logic devices Low voltage Circuit simulation cmos logic circuits Semiconductor device modeling cmos digital integrated circuits

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A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm cmos

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric fo...

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IEEE International Conference on Solid-State circuits (ISSCC)

作者： Amit Agarwal Sanu K Mathew Steven K Hsu Mark A Anders Himanshu Kaul Farhana Sheikh Rajaraman Ramanarayanan Suresh Srinivasan Ram Krishnamurthy Shekhar Borkar Intel Hillsboro OR

A 32 nm on-die fine-grained reconfigurable fabric for DSP/media accelerators is fabricated and occupies a 0.076 mm 2 die. The optimized hybrid arithmetic configurable logic blocks with self-decoded look-up tables, ultra-low voltage PVT-tolerant register file circuits and dual-supply operation help enable a 2.4 GHz nominal performance at 1.0 V and 320 mV-to-1.2 V dynamic voltage range. The peak energy efficiency is 2.6TOPS/W when measured at 340 mV and 50°C.

关键词： Fabrics Digital signal processing Voltage Arithmetic cmos logic circuits Reconfigurable logic logic circuits Registers Dynamic range Energy efficiency

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Low-power split-path data-driven dynamic logic

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IET circuits DEVICES & SYSTEMS 2009年第6期3卷 303-312页

作者： Frustaci, F. Lanuzza, M. Zicari, P. Perri, S. Corsonello, P. Univ Calabria Dept Elect Comp Sci & Syst I-87036 Arcavacata Di Rende CS Italy

Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 x 16 bit Booth multiplier realised with STMicroelectronics 65 nm 1V cmos technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.

关键词： clocks clock signal clock distribution network booth multiplier cmos static logic gates functions split-path D3L low-power split-path data-driven dynamic logic propagation path delay logic gates STMicroelectronics cmos technology size 65 nm energy-delay product low-power electronics dynamic domino logic cmos logic circuits power consumption data-pre-charged dynamic logic

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Effect of glitches against masked AES S-box implementation and countermeasure

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IET INFORMATION SECURITY 2009年第1期3卷 34-44页

作者： Alam, M. Ghosh, S. Mohan, M. J. Mukhopadhyay, D. Chowdhury, D. R. Gupta, I. S. Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur 721302 W Bengal India

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in cmos circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in cmos circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.

关键词： INSPEC: Controlled Indexing vectors cmos logic circuits cryptography delays masks SPICE INSPEC: Non-Controlled Indexing SPICE differential power analysis AES algorithm logic circuits cryptographic algorithms cmos circuits masked circuits leakage combinational path delay vectors balanced masked S-box circuit

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Total-Dose Worst-Case Test Vectors for Leakage Current Failure Induced in Combinational circuits of Cell-Based ASICs

Total-Dose Worst-Case Test Vectors for Leakage Current Failu...

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26th National Radio Science Conference (NRSC 2009)

作者： Abou-Auf, Ahmed A. American Univ Dept Elect Engn Cairo Egypt

We developed a methodology for identifying worst-case test vectors for leakage current failure induced in combinational circuits of cell-based ASICs induced by total-dose. This methodology is independent on the design... 详细信息

ISBN: (纸本)9781424442140

关键词： Circuit testing Leakage current Combinational circuits cmos logic circuits Electronic equipment testing Application specific integrated circuits Circuit faults MOSFETs logic gates Hardware design languages

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A High-Speed, Hierarchical 16x16 Array of Array Multiplier Design

A High-Speed, Hierarchical 16x16 Array of Array Multiplier D...

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International Conference on Multimedia, Signal Processing and Communication Technologies

作者： Asati, Abhijit Chandrashekhar BITS EEE Grp Pilani Rajasthan India CEERI Pilani Rajasthan India

ISBN: (纸本)9781424436033

Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of 0 (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. Some hybrid architectures called 'array of array' multipliers have intermediate performance. These multipliers have a time complexity better than array multipliers, and therefore becomes an obvious choice for higher performance multiplier designs of moderate operand sizes. In this paper a 16x16 unsigned 'array of array' multiplier circuit is designed with hierarchical structure and implemented using conventional cmos logic in 0.6 mu m, N-well cmos process (SCN_SUBM, lambda=0.3) of MOSIS. The proposed multiplier implementation shows large reduction in propagation delay and the average power consumption (at 20MHz) as compared to 16-bit Booth encoded Wallace tree multiplier by F Jalil [3]. The total transistor count, maximum instantaneous power, leakage power, core area, total routing length and number of vias are also presented.

关键词： cmos logic circuits Routing Very large scale integration cmos process Encoding Degradation logic arrays Digital signal processing Hardware Delay

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Modeling and analysis of loading effect in leakage of nano-scaled bulk-cmos logic circuits 05

Modeling and analysis of loading effect in leakage of nano-s...

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Design, Automation and Test in Europe Conference and Exhibition (DATE 05)

作者： Mukhopadhyay, S Bhunia, S Roy, K Purdue Univ Dept ECE W Lafayette IN 47907 USA

ISBN: (纸本)0769522882

In nanometer scaled cmos devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power in a logic circuit. Leakage components interact with each other in device level (through device geometry, doping profile) and also in the circuit level (through node voltages). Due to the circuit level interaction of the different leakage components, the leakage of a logic gate strongly depends on the circuit topology i.e. number and nature of the other logic gates connected to its input and output. In this paper, for the first time, we have analyzed loading effect oil leakage and proposed a method to accurately estimate the total leakage in a logic circuit, from its logic level description considering the impact of loading and transistor stacking.

关键词： logic circuits logic gates logic devices Semiconductor device modeling Nanoscale devices cmos logic circuits Geometry Doping profiles Voltage Circuit topology

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Implementation of ratiometric algorithm to compute partial pressure of Oxygen for a blood oxygen analyser

Implementation of ratiometric algorithm to compute partial p...

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International Symposium on Integrated circuits (ISIC)

作者： Nikhil Joglekar Ronny Veljanovski Aladin Zayegh School of Electrical Engineering Faculty of Health Engineering and Science Victoria University Melbourne Australia

This paper presents the implementation of ratiometric algorithm based on the Stern-Volmer principle to compute partial pressure of oxygen. The algorithm block sits in a novel bio-signal processor designed for a portable blood oxygen analyzer. The key design constraints of the equation implementation are accuracy (to compete with the traditional blood gas analyzer) and power consumption (to make the whole device portable). All of the arithmetic and logic units have been implemented in a 16-bit floating point format and mapped to 0.35 um cmos design library using Synopsys Design Analyzer. The addition and multiplication units are implemented using K.C. Chang's algorithm while the division unit is implemented using Euler's algorithm.

关键词： Oxygen Blood Algorithm design and analysis Process design Equations Energy consumption Floating-point arithmetic cmos logic circuits logic devices logic design

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Asynchronous logic for high variability nano-cmos

Asynchronous logic for high variability nano-CMOS

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IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Alain J. Martin California Institute of Technology Pasadena CA USA

ISBN: (纸本)9781424450909;9781424450916

At the nanoscale level, parameter variations in fabricated devices cause extreme variability in delay. Delay variations are also the main issue in subthreshold operation. Consequently, asynchronous logic seems an ideal, and probably unavoidable choice, for the design of digital circuits in nano cmos or other emerging technologies. This paper examines the robustness of one particular asynchronous logic: quasi-delay insensitive or QDI. We identify the three components of this logic that can be affected by extreme variability: staticizer, isochronic fork, and rings. We show that staticizers can be eliminated, and isochronic forks and rings can be made arbitrarily robust to timing variations.

关键词： cmos logic circuits logic devices Delay Robustness Nanoscale devices logic design Digital circuits cmos digital integrated circuits cmos technology Timing

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Ultra low-voltage switched current mirror

Ultra low-voltage switched current mirror

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IEEE Design and Diagnostics of Electronic circuits and Systems (DDECS)

作者： Yngvar Berg Omid Mirmotahari Microelectronic systems Department of Informatics University of Oslo Norway

In this paper we present a continuous time ultra low voltage current mirror based on clocked semi-floating-gate transistors used in low-voltage digital cmos circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 250 mV and in continuous time. The current mirror performs an auto zero (chopper) function. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm cmos process. We have included an ultra low voltage current mirror with adjustable current levels.

关键词： Mirrors Low voltage cmos technology Threshold voltage cmos logic circuits cmos process Analog circuits Clocks Circuit simulation logic circuits

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