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检索条件"主题词=CMOS Logic Circuits"

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Technology roadmap for 22nm and beyond

Technology roadmap for 22nm and beyond

引用

International Workshop on Electron Devices and Semiconductor Technology (EDST)

作者： Hiroshi Iwai Frontier Research Canter Tokyo Institute of Technology Yokohama Japan

logic cmos technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for cmos circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.

关键词： cmos technology Delay cmos logic circuits MOSFETs FETs Energy consumption Lithography Electron devices logic devices Application specific integrated circuits

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Design and implementation of scalable, transparent threads for multi-core media processor 09

Design and implementation of scalable, transparent threads f...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Takeshi Kodaka Shunsuke Sasaki Takahiro Tokuyoshi Ryuichiro Ohyama Nobuhiro Nonogaki Koji Kitayama Tatsuya Mori Yasuyuki Ueda Hideho Arakida Yuji Okuda Toshiki Kizu Yoshiro Tsuboi Nobu Matsumoto Center of Semiconductor Research and Development Semiconductor Company Toshiba Corporation Kawasaki Kanagawa Japan

ISBN: (纸本)9783981080155

In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the number of cores, and the application program is not affected by the actual number of cores. For the performance efficiency, we designed the threads so that they do not suspend and that they do not start their execution until the data necessary for them are available. We implemented our design using three modules: the dependency controller, which controls dependencies among threads, the thread pool, which manages the ready threads, and the thread dispatcher, which fetches threads from the pool and executes them on the core. Our design and implementation provide efficient thread scheduling with low overhead. Moreover, by hiding the actual number of cores, it realizes transparency. We confirmed the transparency and scalability of our scheme by applying it to the H.264 decoder program. With this scheme, modification of application program is not necessary even if the number of cores changes due to disparate requirements. This feature makes the developing time shorter and contributes to the reduction of the developing cost.

关键词： Yarn Pipeline processing cmos logic circuits Parallel processing Multicore processing Scalability Decoding Costs Hardware VLIW

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A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock

A Low Power Architecture to Extend the Tuning Range of a Qua...

引用

International Conference on VLSI Design

作者： Ramen Dutta T.K. Bhattacharyya Electronics and Electrical Communication Engineering Department Indian Institute of Technology Kharagpur Kharagpur India

A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1 mW from 1.2 V supply voltage at 3 GHz input frequency in 90 nm cmos technology. The output jitter contribution by this circuit is 2 ps and 0.15 ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8 GHz for differential clock and 2.4 GHz for quadrature clock.

关键词： Clocks Frequency Tuning Energy consumption cmos technology Voltage-controlled oscillators Circuit optimization logic gates cmos logic circuits Circuit simulation

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A performance comparison on asynchronous matched-delay templates

A performance comparison on asynchronous matched-delay templ...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Kok-Leong Chang Bah-Hwee Gwee Yuanjin Zheng Centre of Integrated Circuits and Systems Nanyang Technological University Singapore Institute of Microelectronics Integrated Circuits and Systems Laboratory Singapore

ISBN: (纸本)9781424438273

The motivation for asynchronous logic at this juncture of cmos technology is the issues of power density, process variation and integration limit, where synchronous logic is facing a myriad of problems. Asynchronous templates are the fundamental building blocks of asynchronous circuits and systems, and together with asynchronous EDA tools enable the design of complex systems at a high level of abstraction (similar to the RTL-to-GDSII flow in synchronous design). However, akin to the impact of library cells to the overall system performance in the conventional synchronous flow, the diverse availability of asynchronous template libraries requires prudent contemplation. Therefore in this paper, the most eminent matched-delay asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design figure of merits (FOMs) - template area, static/dynamic capacity, cycle time, latency, throughput and Et 2 . The most aggressive template (GasP) can reach a maximum throughput of 5 Giga items/s on 0.13 mum @ 1.2 V.

关键词： cmos logic circuits cmos technology Libraries Throughput cmos process Asynchronous circuits Electronic design automation and methodology System performance Availability Delay

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A hybrid cmos/magnetic tunnel junction approach for nonvolatile integrated circuits

A hybrid CMOS/magnetic tunnel junction approach for nonvolat...

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Symposium on VLSI Technology

作者： Hideo Ohno Laboratory of Nanoelectronics and Spintronics Research Institute of Electrical Communication University of Tohoku Sendai Japan

Magnetic tunnel junction (MTJ), a spintronics device, offers nonvolatile memory capable of fast-read/write with high endurance together with back end of the line (BEOL) compatibility. These features combined with the cmos technology offer not only a non-volatile, high density, and fast random access memory, but also a possibility of constructing a cmos logic circuit having unprecedented low power capability and compactness. The author describe here the development of MTJ, in particular the giant tunnel magnetoresistance of MgO-barrier MTJ and current-induced magnetization switching, basic hybrid cmos/MTJ circuits, and prospects of the current approach along with the remaining challenges.

关键词： Magnetic tunneling cmos integrated circuits Hybrid integrated circuits cmos memory circuits Nonvolatile memory cmos logic circuits cmos technology Magnetoelectronics Integrated circuit technology Random access memory

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Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic

Design of a 64-bit low-energy high-performance adder using d...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Pierce Chuang David Li Manoj Sachdev Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada

ISBN: (纸本)9781424438273

In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive power dissipation in the DFTL approach. A 64-bit Sklansky carry-merge adder is used as a benchmark comparison between different logic styles including DFTL, CDL, dynamic, and static logic. Simulation results reveal that the proposed work achieves better performance and is more energy efficient than the other logic styles for high performance adder designs.

关键词： logic design MOS devices logic gates Energy consumption Timing cmos technology MOSFETs Low voltage cmos logic circuits Performance analysis

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Two phase clocked adiabatic static cmos logic

Two phase clocked adiabatic static CMOS logic

引用

IEEE International Symposium on System-on-Chip

作者： Nazrul Anuar Yasuhiro Takahashi Toshikazu Sekine Graduate School of Engineering Gifu University Gifu Japan Department of Electrical and Electronic Engineering Gifu University Gifu Japan

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static cmos logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static cmos at transition frequencies of 10-100 MHz respectively.

关键词： Clocks cmos logic circuits Power supplies Diodes cmos technology logic circuits Energy consumption logic devices Energy dissipation Voltage

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Novel reversible division hardware

Novel reversible division hardware

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Midwest Symposium on circuits and Systems (MWSCAS)

作者： Noor Muhammed Nayeem Adnan Hossain Mutasimul Haque Lafifa Jamal Hafiz M. Hasan Babu Department of Computer Science and Engineering University of Dhaka Dhaka Bangladesh

This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.

关键词： Hardware Costs logic design Quantum computing Sequential circuits cmos logic circuits DH-HEMTs Application software logic circuits Automata

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Clocked semi-floating-gate ultra low-voltage current multiplier

Clocked semi-floating-gate ultra low-voltage current multipl...

引用

European Conference on Circuit Theory and Design, ECCTD

作者： Y. Berg O. Mirmotahari Microelectronic systems Department of Informatics University of Oslo Oslo Norway

In this paper we present a ultra low voltage current mode multiplier. The current multiplier is based on a clocked semi floating gate design strategy used for ultra low voltage digital and analog design. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. A current multiplier able to operate at supply voltages below 200 mV is presented and simulated data are provided. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm cmos process.

关键词： Clocks Low voltage cmos technology Analog circuits cmos logic circuits Threshold voltage Circuit simulation cmos process MOSFETs cmos analog integrated circuits

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Presentation of new architecture for reduction of power dissipation in nano hybrid chip

Presentation of new architecture for reduction of power diss...

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Workshop on Power Electronics and Intelligent Transportation System, PEITS

作者： Pooria Mostafalu Hadi Jahanirad Department of ECE Iran University of Science and Technology Tehran Iran

In this paper we present an architecture for nanowire layer in FPNI which is include switch boxes concept. The FPNI improves the Field-Programmable Gate Array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches which decreases both the area and power consumption of the circuit. In this paper we present an approach to building an FPNI chip which is similar to cmos FPGA. By applying genetic algorithm optimization tool, a delay optimized circuit is implemented in FPNI. The power dissipation in two chips are compared to emphasize the benefits of this new architecture.

关键词： Power dissipation Capacitance Integrated circuit interconnections cmos logic circuits Conductivity Delay Nanoscale devices Wires Dielectric constant Copper

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