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检索条件"主题词=CMOS Logic Circuits"

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A cmos based logic driver design for a 16 × 16 multiplexer based read-out array for infrared microbolometers

A CMOS based logic driver design for a 16 × 16 multiplexer ...

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AFRICON Conference

作者： Pieter Johannes Visser Johan Schoeman Monuko du Plessis Department of Electrical Electronic and Computer Engineering University of Pretoria South Africa

Infrared imaging detectors require highly temperature sensitive sensors placed in a focal plane array. Due to the nature of these sensors, they can not simply be biased continuously, as this causes unwanted self heating that distorts the desired measurement. This is typically overcome by the use of pulse based biasing systems to reduce the time during which a sensor can measure incoming radiation, but this in turn requires a careful timing analysis and synchronisation in the design. This paper presents parts of the simulation design of a fully-integrated cmos time-division analogue multiplexer circuit serving both as a biasing and a read-out circuit for a 16 times 16 array of uncooled microbolometers. The contribution and emphasis lies in the design of a control logic driver for a multiplexer based read-out circuit that not only ensures synchronous operation, but in doing so, also ensures that the sensors are biased for as short a period as possible. The initial design was completed for fabrication in a standard 0.35 mum cmos process. Simulation results indicate a fully synchronous system, and the specific architecture implemented has reduced the biasing time of each element to less than 0.2% of the read-out time for an entire frame.

关键词： logic arrays cmos logic circuits logic design Multiplexing Sensor arrays Temperature sensors Distortion measurement Pulse measurements Circuit simulation cmos image sensors

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A robust synchronized 2N2P LC oscillator with a shut-down mode for adiabatic logic circuits

A robust synchronized 2N2P LC oscillator with a shut-down mo...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Philip Teichmann Jurgen Fischer Doris Schmitt-Landsiedel Institute of Technical Electronics Technische Universität München Munchen Germany

ISBN: (纸本)9781424438273

Adiabatic logic saves energy compared to static cmos by charging the outputs efficiently and by recovering charge from the outputs. For the most promising adiabatic logic families a four phase power-clock is used, that can be generated in an energy efficient manner by using a synchronized 2N2P LC oscillator. Different input patterns to the circuit lead to different capacitive loads seen by the oscillator. A method to investigate the impact of the pattern-induced capacitive variations on the LC oscillator is presented in this paper. The circuit should be disconnected from the power-clock in idle times, when no data is processed, as adiabatic logic consumes energy also if no change occurs in the input data. We propose an easy to implement, powerful and fast method to switch off the oscillator by holding the synchronization signals constant. This makes adiabatic systems even more energy efficient.

关键词： Robustness Oscillators logic circuits Frequency synchronization cmos logic circuits Capacitance Power generation Energy efficiency Voltage Switches

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A high-speed differential receiver with low-power interleaved direct decision feedback equalizer

A high-speed differential receiver with low-power interleave...

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International SoC Design Conference, ISOCC

作者： Min-Sik Han Sang-Hyuk Yang Suki Kim Shin-Il Lim Department of Electrical Engineering Korea University Seoul South Korea Department of Electrical & Computer Engineering Seokyeong University Seoul South Korea

ISBN: (纸本)9781424450343;9781424450350

A high-speed differential receiver with low-power interleaved direct decision feedback equalizer (DFE) is proposed and designed with a 0.18 um cmos process. To save the power consumption, the new feedback topology is introduced. This architecture feeds back the previous bit to the proposed latch block. As a result, the adder blocks can be removed obtaining the low-power interleaved direct DFE. The current mode logic (CML) latch with embedded adder is used to reduce power consumption.

关键词： Decision feedback equalizers Intersymbol interference Energy consumption Crosstalk Bandwidth Adders Interleaved codes Power engineering and energy cmos process cmos logic circuits

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Optimization of sub-100nm transistor gate sidewall spacer process for high-performance applications

Optimization of sub-100nm transistor gate sidewall spacer pr...

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IEEE Conference on Electron Devices and Solid-State circuits

作者： Chun-Jen Weng The Department of Technology Management Leader University Taiwan

As the technology node advances to the next generation, one of the biggest challenges is to achieve minimum pitch while maintaining device performance. This paper describes the details of a novel manufacturing process integration of complementary metal oxide semiconductor (cmos) transistor architecture, which is incorporated into a sub-micron logic technology on 300 mm wafers. As the gate length is scaling down, the spacer design for cmos transistor becomes increasingly critical manufacturing process. Moreover, the material of the sidewall spacer itself plays an important role, and its impact on device performance has been intensively discussed. Fabrication process results show that the offset spacer configuration and width can effectively increase the on-state driving current and reduce the off-state leakage current off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate spacer extension structure. A novel semiconductor fabrication process on gate spacer technology and electrical performance of nano-meter gate structure was included.

关键词： Space technology Transistors cmos technology Manufacturing processes cmos process Fabrication cmos logic circuits logic devices Semiconductor materials Leakage current

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Integration of cmos, single electron transistors, and quantumdot cellular automata

Integration of CMOS, single electron transistors, and quantu...

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IEEE Nanotechnology Materials and Devices Conference (NMDC)

作者： Aaron A. Prager Alexei O. Orlov Gregory L. Snider University of Notre Dame Notre Dame IN USA

The physical limits associated with cmos devices require the development of new computational architectures. Quantum-dot cellular automata (QCA) offers a low power, high-speed computational architecture. This paper demonstrates the integration of cmos, QCA, and SET technologies on a single silicon die. A capacitive voltage divider is used to reduce standard cmos logic voltage levels to millivolt control voltages for a two-dot QCA cell. SET electrometers are used to read the state of the QCA cell, and the resultant signal is applied to a cmos voltage comparator, which provides a cmos logic level voltage output.

关键词： Single electron transistors Quantum cellular automata Computer architecture cmos logic circuits Voltage Physics computing Quantum dots Quantum computing cmos technology Silicon

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Ultra low voltage and high speed cmos carry generate circuits

Ultra low voltage and high speed CMOS carry generate circuit...

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European Conference on Circuit Theory and Design, ECCTD

作者： Y. Berg O. Mirmotahari Microelectronic systems Department of Informatics University of Oslo Oslo Norway

In this paper we present different ultra low-voltage cmos carry generate circuits. The circuits may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuits show an improved performance compared to complementary cmos in terms of delay. Preliminary results indicate a reduced delay to approximately 1/10 of a complementary cmos design. Simulated data for a ST 90 nm cmos process are included.

关键词： Low voltage Threshold voltage cmos process cmos logic circuits Capacitance Inverters Delay logic circuits Energy consumption MOSFETs

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Low power FFT design for wireless communication systems

Low power FFT design for wireless communication systems

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IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Mohd Shamian Zainal Shingo Yoshizawa Yoshikazu Miyanaga Graduate School of Information Science and Technology Hokkaido University Japan

This paper presents a new study over logics circuit operation in subthreshold and threshold region. cmos circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate for high frequency and with low voltage source. A FFT processor is the most critical part on speed in multi-carrier orthogonal frequency division multiplexing (OFDM) communication systems. In these systems, power dissipation is usually one of the major concerns. In this report, we evaluate the low-power consumption of a radix-2 pipeline FFT and concurrent FFT with low voltage power supply. FFT simulation results clearly show that low voltage is not a barrier for logic design to operate at high frequency.

关键词： Wireless communication Low voltage cmos logic circuits OFDM logic circuits Semiconductor device modeling Power system modeling Presses Process design Power dissipation

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Tree multipliers with modified Booth algorithm based on adiabatic CPL

Tree multipliers with modified Booth algorithm based on adia...

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International Symposium on Integrated circuits (ISIC)

作者： Binbin Liu Jianping Hu Faculty of Information Science and Technology Ningbo University Ningbo Zhejiang China

This paper describes an adiabatic tree multiplier based on modified booth algorithm, which operates on four-phase power clocks. It is composed of booth encoder, partial product generators followed by booth encoding, a complementary decoder that is required by the partial product generator, Wallace trees with 4-2 compressors, and a final carry-lookahead adder. All circuits are realized by CPAL (complementary pass-transistor adiabatic logic) circuits with TSMC 0.18 ¿m cmos process technology. Compared with its cmos counterpart based on conventional logic circuits, the four-phase adiabatic multiplier attains energy savings of 86.6% at 50 MHz and 72.8% at 300 MHz, respectively.

关键词： cmos logic circuits logic arrays Clocks Compressors Encoding Decoding cmos technology logic circuits Signal processing algorithms Adders

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Evaluation of a DPA-Resistant Prototype Chip

Evaluation of a DPA-Resistant Prototype Chip

引用

Annual Computer Security Applications Conference

作者： Mario Kirschbaum Thomas Popp Institute of Applied Information Processing and Communications Graz University of Technology Graz Austria

ISBN: (纸本)9781424453276

The recently proposed masked logic style iMDPL seems to eradicate many of the latest points of criticism against masked logic styles in general. By means of a prototype chip containing different implementations we analyze the DPA resistance of iMDPL. Furthermore we compare the results with the logic styles' predecessor MDPL, which verifiably suffers from an effect called early propagation. We also investigate iMDPL regarding an advanced attack approach that claims to be able to almost completely remove the effect of masking in masked logic styles.

关键词： Prototypes Energy consumption logic design cmos logic circuits Cryptography Switches Microcontrollers Computer security Application software Information processing

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Low temperature integration of hybrid cmos devices on plastic substrates

Low temperature integration of hybrid CMOS devices on plasti...

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Flexible Electronics and Displays Conference and Exhibition

作者： S. Gowrisanker M.A. Quevedo-Lopez H. N. Alshareef B. Gnade S. Venugopal R. Krishna K. Kaftanoglu D. Allee University of Texas at Dallas Richardson Texas Flexible Display Center at Arizona State University Tempe Arizona USA

ISBN: (纸本)9781424443383

The development of flexible complimentary metal-oxide-semiconductor (cmos) circuits reduces power consumption by ~50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate cmos circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180degC and 120degC for the p-type TFTs. cmos circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the cmos integration process flow are 1.0 and 0.05 cm 2 /V-s, respectively. Threshold voltages (V t ) are 3.89 V for nMOS and -1.89 V for pMOS. The voltage transfer curve of the cmos inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR cmos gates are reported.

关键词： Temperature Plastics Thin film transistors Substrates cmos process Inverters MOS devices cmos logic circuits cmos digital integrated circuits Flexible printed circuits

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