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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是371-380 订阅

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A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm cmos

A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13...

引用

International Symposium on VLSI Design, Automation and Test

作者： Chen-Kang Ho Hao-Chiao Hong Department of Electrical and Control Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781424427819

This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13 mum cmos. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6 GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the -1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively.

关键词： Circuit testing Ash Sampling methods cmos logic circuits Bandwidth cmos technology Dynamic range logic circuits Circuit noise Resistors

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Fully tunable UWB pulse generator with zero DC power consumption

Fully tunable UWB pulse generator with zero DC power consump...

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IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)

作者： R. Vauche S. Bourdel N. Dehaese O. Fourquin J. Gaubert IM2NP and CNRS IM2NP (UMR 6242) Aix Marseille University Marseilles France

The design of a fully tunable pulse generator using only logic cells is presented and simulated with 0.13 mum standard cmos process. The generator is based on the elementary pulse combination and can synthesize different UWB pulse shapes. The generator uses logic gates to achieve the elementary pulses and a H-bridge to make the combination which leads to a zero DC power consumption. To achieve FCC compliant pulse having 2 V PP magnitude the generator consumes 140 pJ by pulse using 1.2 V supply voltage.

关键词： Pulse generation Energy consumption cmos logic circuits Pulse shaping methods logic design cmos process Shape DC generators Power generation logic gates

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A study of sub-threshold digital circuits for wireless communication systems

A study of sub-threshold digital circuits for wireless commu...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Mohd Shamian Zainal Shingo Yoshizawa Yoshikazu Miyanaga Graduate School of Information Science and Technology Hokkaido University Sapporo Japan

Digital circuit designs in sub-threshold region have been studied in recent years. Their works focus on special purpose for some digital applications in low frequency. This paper proposed modeling analysis of each cmos logic cell operating at sub-threshold region. We explore the delays and power dissipation of logic cell and make scaled factors mapping from typical voltage to sub-threshold voltage conditions. We evaluated the minimum requirement for 4 bits, 6 bits and 10 bits orthogonal frequency division multiplexing (OFDM) demodulator to operate in sub-threshold region. The simulation results are characteristics of OFDM wireless communication system when it operates at low voltage. It also clearly shows that low voltage is not a barrier for large-scale digital circuits to operate under the threshold voltage.

关键词： Digital circuits Wireless communication OFDM cmos logic circuits Low voltage Semiconductor device modeling Power system modeling Delay Power dissipation Demodulation

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Defect Mapping and Adaptive Configuration of Nanoelectronic circuits Based on a CNT Crossbar Nano-Architecture

Defect Mapping and Adaptive Configuration of Nanoelectronic ...

引用

International Conference on Computer Communications and Networks (ICCCN)

作者： Bao Liu Electrical and Computer Engineering Department University of Texas San Antonio San Antonio TX USA

Successful fabrication of a variety of nanoscale devices leads to research on nanoscale device integration, nano-architecture exploration, and nanoelectronic design techniques. This paper proposes a complete set of linear complexity catastrophic defect mapping techniques for CNT crossbar nano-architecture, as well as an adaptive CNT matching method for double gate CN-FETs in the presence of CNT misalignment. Combined with adaptive nano-addressing method, these proposed techniques enable adaptive configuration of nanoelectronic circuits of correct functionality, performance, and reliability based on the CNT crossbar nano-architecture.

关键词： Nanoscale devices CNTFETs Carbon nanotubes Semiconductor diodes cmos logic circuits MOSFETs Fabrication Very large scale integration logic arrays Integrated circuit interconnections

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Clocked semi-floating-gate pseudo differential pair for low-voltage analog design

Clocked semi-floating-gate pseudo differential pair for low-...

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European Conference on Circuit Theory and Design, ECCTD

作者： Y. Berg O. Mirmotahari Microelectronic systems Department of Informatics University of Oslo Oslo Norway

In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm cmos process with a transistor threshold voltage equal to 250 mV is included.

关键词： Clocks Low voltage cmos technology cmos logic circuits Analog circuits cmos process Threshold voltage MOSFETs MOS devices Circuit simulation

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Measurement of power supply noise tolerance of self-timed processor

Measurement of power supply noise tolerance of self-timed pr...

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IEEE Design and Diagnostics of Electronic circuits and Systems (DDECS)

作者： Kunihiro Asada Taku Sogabe Toru Nakura Makoto Ikeda Department of Electronic Engineering University of Tokyo Bunkyo Tokyo Japan VLSI Design and Education Center Bunkyo Tokyo Japan

We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18mum cmos. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.

关键词： Power measurement Noise measurement Power supplies Circuit noise cmos process Process design cmos logic circuits logic design logic circuits Error analysis

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Frame-Scheduling for Input-Queued Switches with Energy Reconfiguration Costs

Frame-Scheduling for Input-Queued Switches with Energy Recon...

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GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference

作者： Andrea Bianco Paolo Giaccone Marco Ricca Dipartimento di Elettronica Politecnico di Turino Italy

We consider a slotted input-queued switch with a crossbar-like switching fabric. In each time-slot, a centralized scheduler determines a switching fabric configuration to transfer packets. We consider the energy consumption needed to configure the switching fabric and we assume that the energy depends on the number of modifications in the switching configuration in two consecutive time-slots. We address the problem of scheduling a set of packets to minimize the required energy while preserving high throughput. We reduce the overall problem to the combination of two different optimization problems. We propose a family of algorithms to solve the problem and we discuss their energy-throughput performance.

关键词： Switches Costs Fabrics Energy consumption Packet switching Throughput Scalability cmos technology logic gates cmos logic circuits

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Design and Development of Clocked Transmission Gate Cross-Coupled Adiabatic Circuit

Design and Development of Clocked Transmission Gate Cross-Co...

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International Conference on Advances in Computing, Control, & Telecommunication Technologies (ACT)

作者： Aminul Islam Mohd. Hasan Department of ECE Birla Institute of Technology Ranchi Jharkhand India Department of Electronics Engineering Zakir Hussain College of Engineering and Technology Aligarh Muslim University Aligarh Uttar Pradesh India

In this paper, a novel clocked transmission gate cross-coupled adiabatic (CTGCA) circuit is proposed based on dual phase power clock generator. Unlike conventional power supply used in static cmos logic, adiabatic logic requires AC-type supply voltage to recycle the energy stored on the load capacitance. In this paper, first a dual-phase sinusoidal power clock generator (DSPCG) is reviewed and further developed which is used in CTGCA circuit. Simulations are carried out using Spectre of Cadence. The 0.6 ¿m cmos technology has been used for simulation. Simulation result shows significant energy savings compared to static cmos counterpart.

关键词： Clocks cmos logic circuits Power supplies Voltage Capacitance cmos technology Power generation Recycling Circuit simulation logic circuits

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A 90-nm cmos embedded low power SRAM compiler

A 90-nm CMOS embedded low power SRAM compiler

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International Conference on ASIC

作者： Zhao-Yong Zhang Chia-Cheng Chen Jian-Bin Zheng Memory Design Department AiceStar Technology Corporation Suzhou China Module Intellectual Property Development Faraday Technology Corporation Hsinchu Taiwan

In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active power. Particular emphasis was put to decrease standby power consumption in word line driver. The forced-stack devices as pulse generation element was introduced for sensing enable. This guarantees SRAM can work in low voltage without losing design margin. A test-chip with 17 embedded SRAMs has been fabricated in UMC 90-nm low leakage cmos logic process.

关键词： Random access memory Pulse generation Circuit testing logic testing cmos process cmos logic circuits Circuit synthesis Driver circuits logic arrays Voltage

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A Speed-Improved Architecture for cmos Programmable Divider

A Speed-Improved Architecture for CMOS Programmable Divider

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International Conference on Innovative Computing, Information and Control (ICICIC)

作者： Ching-Wen Hsu Yu-Sheng Lin Chun-Lin Lu Yeong-Her Wang Kuo-Sheng Cheng Department of Computer and Communication Kun Shan University Taiwan Department of Electrical Engineering National Cheng Kung University Taiwan

ISBN: (纸本)9781424455430

This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-by-two frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-mum cmos process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

关键词： Frequency conversion Switches logic circuits Inverters MOS devices Switching circuits Parasitic capacitance cmos logic circuits cmos process Circuit simulation

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