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检索条件"主题词=CMOS Logic Circuits"

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A scheme of logic self repair including local interconnects

A scheme of logic self repair including local interconnects

引用

IEEE Design and Diagnostics of Electronic circuits and Systems (DDECS)

作者： T. Koal D. Scheit H. T. Vierhaus Computer Science Institute Brandenburg University of Technology Cottbus Germany

Technology forecasts concerning the development of cmos technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in the field of application are becoming a must. The architecture introduced in this paper includes mechanisms for logic self repair that may also cover local interconnects.

关键词： cmos technology Hardware Field programmable gate arrays cmos logic circuits Production Redundancy Power system interconnection Switches Computer science Technology forecasting

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A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital cmos process

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digit...

引用

International Symposium on VLSI Design, Automation and Test

作者： Chun-Cheng Liu Yi-Ting Huang Guan-Ying Huang Soon-Jyh Chang Chung-Ming Huang Chih-Haur Huang Department of Electrical Engineering National Cheng Kung University Tainan County Taiwan Himax Technologies Inc. Tainan County Taiwan

ISBN: (纸本)9781424427819

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost cmos integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-mum 1P5M digital cmos technology, the ADC only occupies 0.032 mm 2 active area.

关键词： cmos process Switches Clocks cmos technology Energy consumption cmos logic circuits Switched capacitor networks Voltage Analog-digital conversion Sampling methods

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A double-scroll based true random number generator with power and throughput adjustable

A double-scroll based true random number generator with powe...

引用

International Conference on ASIC

作者： Fuqiang Cao Shuguo Li Institute of Microelectronics Tsinghua University Beijing China

A new double-scroll chaotic oscillator circuit is proposed to design a true random number generator (TRNG) in cmos process. The proposed oscillator is base on differential amplifiers by only MOS transistors and especially suitable to be integrated in standard logic process. The power of the oscillator is adjustable from 369 ¿W to 2.7 ¿W with different speed levels, proving low power operation ability and wide adjusting range. A low cost TRNG is realized and the quality of the output sequences is evaluated when the whole circuit consumes 53 ¿W. The sequences pass the NIST FIPS140-1 standard randomness test at 1 MHz clock frequency, showing better throughput-power efficiency compared to other papers.

关键词： Random number generation Throughput Oscillators Chaos cmos process Differential amplifiers MOSFETs cmos logic circuits Costs NIST

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Fast and waveform independent characterization of current source models

Fast and waveform independent characterization of current so...

引用

IEEE International Workshop on Behavioral Modeling and Simulation (BMAS)

作者： Christoph Knoth Veit B. Kleeberger Petra Nordholz Ulf Schlichtmann Institute for Electronic Design Automation Technische Universität Munchen Germany Infineon Technologies Neubiberg Germany

A fast characterization method for current source models (CSM) is proposed. It analyses the given transistor netlist of cmos logic cells to determine both static and dynamic CSM parameters in the same DC simulation. To account for the influence of parasitic elements in large logic cells, an additional low pass filter is inserted to the CSMs. AC analysis is employed to efficiently define its parameters. The characterization is therefore independent of user specified input waveforms. CSMs of industrial gates have been integrated into a standard SPICE simulator, showing high accuracy also for noisy input waveforms. Used in path based timing analysis of ISCAS85 circuits, average errors of 3% have been observed while simulation times could be reduced by a factor of 100.

关键词： Crosstalk Timing Delay Circuit simulation Analytical models Semiconductor device modeling cmos logic circuits Voltage Integrated circuit noise Noise figure

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2009 Symposia on VLSI technology & circuits-conference schedule

2009 Symposia on VLSI technology & circuits-conference sched...

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Symposium on VLSI circuits

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A novel low-power and high-speed dynamic cmos logic circuit technique

A novel low-power and high-speed dynamic CMOS logic circuit ...

引用

National Conference on Radio Science (NSRC)

作者： Sherif M. Sharroush Yasser S. Abdalla Ahmed A. Dessouki El-Sayed A. El-Badawy Department of Elect Eng Faculty of Engineering Port Said Suez-Canal University Egypt Department of Electricity Faculty of Industrial Education Suez Suez-Canal University Egypt Alex High er Institute of Engineering & Technology / Faculty of Engineering Alexandria University Alexandria Egypt

Domino cmos logic finds a wide variety of applications due to their high speed and low device count. In conventional cmos domino logic, either the dynamic-node capacitor, C L is precharged to V DD during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic "0" occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic "1" is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic "0" and logic "1". This technique depends on precharging the dynamic node to V DD /2 instead of V DD during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to V DD or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from V DD /2 to 0 V is much faster and consumes less power consumption than discharging it from V DD to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 mum technology with V DD =1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of "0" and "1" outputs at the expense of an additional silicon area.

关键词： cmos logic circuits logic devices Voltage Energy consumption Irrigation Capacitors Silicon Circuit noise cmos digital integrated circuits cmos memory circuits

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Single Event Effects Tests on the Actel RTAX2000S FPGA

Single Event Effects Tests on the Actel RTAX2000S FPGA

引用

IEEE Workshop on Radiation Effects Data

作者： Jeffrey S. George Rocky Koga Mark Zakrzewski Aerospace Corporation El Segundo CA USA

We present new single event effects testing results for the RTAX2000S field-programmable-gate-array. We tested sequential and combinational logic structures, input/output blocks, and embedded RAM with ions and protons.

关键词： Field programmable gate arrays logic testing logic devices Clocks Connectors Circuit testing NASA Aerospace testing cmos logic circuits logic programming

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Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)

Chip Scale Camera Module (CSCM) using Through-Silicon-Via (T...

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： Hiroshi Yoshikawa Atsuko Kawasaki Tomoaki Iiduka Yasushi Nishimura Kazumasa Tanida Kazutaka Akiyama Masahiro Sekiguchi Mie Matsuo Satoru Fukuchi Katsutomu Takahashi Toshiba Semiconductor Company Limited Yokohama Japan Toshiba Semiconductor Yokohama Japan

Through silicon via (TSV) is one of the necessary technologies for three-dimensional integration of LSIs. Heterogeneous system integration is a good candidate for its application, which includes the "Vision Chip". TSV technology is applied to a cmos imager sensor camera module for mobile handsets and successfully achieves a size reduction of 55% in volume and 36% in footprint, which we refer to as a chip scale camera module (CSCM). To the best of the authors' knowledge, CSCM is the first mass-produced product using TSV technology.

关键词： Cameras Through-silicon vias cmos image sensors Costs Insulation Wiring Wires cmos logic circuits Surface-mount technology Wafer bonding

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Cascaded Time Difference Amplifier using Differential logic Delay Cell

Cascaded Time Difference Amplifier using Differential Logic ...

引用

International SoC Design Conference, ISOCC

作者： Shingo Mandai Toru Nakura Makoto Ikeda Kunihiro Asada Department of Electrical Engineering and Information Systems University of Tokyo Bunkyo Tokyo Japan VLSI Design and Education Center(VDEC) University of Tokyo Bunkyo Tokyo Japan

ISBN: (纸本)9781424450343;9781424450350

We introduce a 4 2 × cascaded time difference amplifier (TDA) using differential logic delay cells with 0.18 ¿m cmos process. By employing differential logic cells for the delay chain instead of cmos logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ± 250 ps input range. Also the charge pump current of PMOS and NMOS unbalance can adjust the TD gain.

关键词： Differential amplifiers Delay effects cmos logic circuits Switches Gain control Signal resolution Propagation delay Inverters Very large scale integration Information systems

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Silicon-on-Sapphire, a replacement for gallium arsenide?

Silicon-on-Sapphire, a replacement for gallium arsenide?

引用

IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

作者： George. P. Imthurn Peregrine Semiconductor Inc. USA

Silicon-on-sapphire (SOS) was invented in 1961 and as such is the first of the SOI technologies. Its original purpose was to provide radiation tolerant circuits for satellites and missiles. Now, SOS is ready to displace gallium arsenide (GaAs) as the technology of choice for RF communications in commercial applications. What are the reasons for this? In this paper, I will share what we have learned at Peregrine semiconductor about how to use cmos for RF devices and why silicon will eventually displace GaAs from many RF applications.

关键词： Gallium arsenide Switches Radio frequency Silicon on insulator technology Voltage cmos logic circuits Decoding FETs Costs Electron mobility

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