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检索条件"主题词=CMOS Logic Circuits"

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Synthesis of Fault Tolerant Reversible logic circuits

Synthesis of Fault Tolerant Reversible Logic Circuits

引用

IEEE circuits and Systems International Conference on Testing and Diagnosis, ICTD

作者： Md. Saiful Islam M. M. Rahman Zerina Begum Mohd. Zulfiquar Hafiz Abdullah Al Mahmud Institute of Information Technology University of Dhaka Dhaka Bangladesh Dept. of Computer Science and Engineering Ahsanullah University of Science and Technology Dhaka Bangladesh

Reversible logic is emerging as an important research area having its application in diverse fields such as low power cmos design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

关键词： Circuit synthesis Fault tolerance logic circuits cmos logic circuits Signal synthesis Quantum computing Optical computing logic gates logic design cmos process

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A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail logic Swing in 90 nm cmos process

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90...

引用

IEEE MTT-S International Microwave Workshop Series (IMWS)

作者： A. Mineyama T. Suzuki H. Ito S. Amakawa N. Ishihara K. Masu Tokyo Institute of Technology Yokohama Japan Fujitsu Laboratories Limited Atsugi Japan

A 9.5 mW 20 Gb/s 40times70 mum 2 inductorless 1:4 DEMUX in 90 nm cmos process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralow-voltage many-core era.

关键词： cmos logic circuits cmos process Latches Clocks Wavelength division multiplexing Threshold voltage Scalability Optical noise Circuit noise Microwave Theory and Techniques Society

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Mixed signal frequency mixers with intermodulation product cancellation

Mixed signal frequency mixers with intermodulation product c...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： William A. Ling Paul P. Sotiriadis Robert Adams Johns Hopkins University Baltimore MD USA Sotekco Electronics LLC Baltimore MD USA Analog Devices Inc.orporated Wilmington MA USA

ISBN: (纸本)9781424438273

We propose a nearly all-digital, broadband frequency mixer which synthesizes a sinewave at the frequency difference of two periodic input square waves. The mixer has high output spurious free dynamic range by cancelling the dominant intermodulation products in the sinewave generation process. Due to its use of almost exclusively digital circuitry, it can easily be integrated with cmos digital circuits. A programmable logic implementation and spectral measurements demonstrate its feasibility and performance.

关键词： Frequency synthesizers Integrated circuit synthesis Signal synthesis Dynamic range cmos digital integrated circuits Digital circuits cmos logic circuits Programmable logic arrays Programmable logic devices Integrated circuit measurements

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Subthreshold leakage reduction: A comparative study of SCL and cmos design

Subthreshold leakage reduction: A comparative study of SCL a...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Armin Tajalli Yusuf Leblebici Microelectronic Systems Laboratory (LSM) Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781424438273

The large subthreshold leakage current of static cmos logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based on an NMOS differential pair that is switching a constant tail bias current between the two output branches while biased at very low current levels. The power consumption of each STSCL gate depends on the tail bias current that can be controlled very well even for current levels in the range of few tens of pico-Amperes. The precise control on the power consumption of each gate, makes this topology very attractive for ultra-low power applications, where the power consumption of conventional static cmos system is practically limited by the subthreshold leakage current. In this work, an analytical approach supported by simulation and measurement results will be presented to study the main issues in design of ultra-low power static cmos and STSCL systems.

关键词： Subthreshold current Energy consumption cmos logic circuits Tail cmos technology Digital systems logic circuits MOS devices Switching circuits Control systems

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Beyond innovation: Dealing with the risks and complexity of processor design in 22nm

Beyond innovation: Dealing with the risks and complexity of ...

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International Electron Devices Meeting (IEDM)

作者： Carl John Anderson IBM Austin TX USA

This paper discusses the importance of discipline and risk management in the design of new high performance microprocessors in advanced technologies. Innovation is very important in these designs but the design costs ... 详细信息

关键词： Technological innovation Process design Microprocessors Circuit synthesis Costs Bipolar transistor circuits Risk management Productivity logic circuits cmos logic circuits

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Ultra-low power subthreshold flip-flop design

Ultra-low power subthreshold flip-flop design

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Sagi Fisher Adam Teman Dmitry Vaysman Alexander Gertsman Orly Yadid-Pecht Alexander Fish VLSI Systems Center Ben-Gurion University of the Negev Beersheba Israel

ISBN: (纸本)9781424438273

In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary cmos logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region, utilizes this current, minimizing power consumption in low-frequency systems. This paper proposes two architectures for implementing flip-flop cells, designed to operate in the subthreshold region. Both cells integrate a gate-diffusion input (GDI) multiplexer in their designs to minimize area and capacitance. Timing parameters of the flip-flops are calculated and techniques for improving the timing characteristics are proposed. The proposed designs are simulated in a standard 90 nm process achieving a power dissipation of 8.4 nW in a typical corner at VDD = 300 mV with a delay of 51.7 nsec.

关键词： Flip-flops Timing Very large scale integration cmos technology Leakage current cmos logic circuits Subthreshold current Digital circuits Energy consumption Multiplexing

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Robust differential asynchronous nanoelectronic circuits

Robust differential asynchronous nanoelectronic circuits

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IEEE International Symposium on Quality Electronic Design

作者： Bao Liu Electrical and Computer Engineering Department University of Texas San Antonio San Antonio TX USA

Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing correctness in the presence of glitches. In this paper, I propose robust differential asynchronous (RDA) circuits, which combine asynchronous circuits for delay insensitiveness, differential logic for redundancy, and error detection codes for resilience. Theoretical analysis and SPICE simulation based on 22 nm cmos Predictive Technology Models show that the proposed RDA circuits achieve much enhanced reliability in (1) logic correctness at the event of a single bit soft error or common multiple bit soft errors by differential logic and error detection codes, and (2) timing correctness for any delay variation given physical proximity of the circuit components, with comparable area overhead to existing asynchronous circuits.

关键词： cmos logic circuits Delay Asynchronous circuits Error correction codes logic circuits Timing Predictive models cmos technology Noise robustness Circuit noise

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Symmetric semi-floating-gate pseudo differential pair for low-voltage analog design

Symmetric semi-floating-gate pseudo differential pair for lo...

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Norchip

作者： Y. Berg Nanoelectronics Department of Informatics University of Oslo Blindern Norway

In this paper we present a symmetric ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm cmos process is included.

关键词： cmos technology Low voltage Clocks MOSFETs cmos logic circuits Analog circuits MOS devices cmos process Threshold voltage cmos analog integrated circuits

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The dynamic model of electrostatic torsion mirror with pull-in consideration for multiphysics behavior anticipation

The dynamic model of electrostatic torsion mirror with pull-...

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Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Yuheon Yi Hiroyuki Fujita Hiroshi Toshiyoshi Institute of Industrial Science University of Tokyo Meguro Tokyo Japan

This study presents a newly developed dynamic model established by MATLAB Simulink that can handle post pull-in behavior of MEMS electrostatic torsional mirror. In addition to the conventional MATLAB Simulink model of the quadratic oscillation system, a mathematical model of displacement limiter has been inserted to represent the pull-in effect in dynamic analysis. Due to the modification, the model has become applicable to both pre- and post pull-in region of electrostatic actuators. Electrical circuits from the MATLAB Simulink library can be combined with the mechanical model and simulated to see multiphysics behavior. The new model has been integrated in the simulation model of self-oscillating MEMS system which has cmos logics, and the versatility in the behavior-level simulation has been verified.

关键词： Mirrors Mathematical model Circuit simulation Micromechanical devices Electrostatic actuators MATLAB Semiconductor device modeling cmos logic circuits cmos image sensors Analytical models

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Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

Design-Space Exploration of Energy-Delay-Area Efficient Coar...

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International Conference on VLSI Design

作者： Sohan Purohit Marco Lanuzza Stefania Perri Pasquale Corsonello Martin Margala Department of Electrical and Computer Engineering University of Massachusetts Lowell USA Department of Electronics Computer Science and Systems University of Calabria Rende Italy

This paper presents the VLSI design of a high data throughput, energy and area efficient data path targeted for DSP and multimedia applications. Three different implementations of the reconfigurable data path using static, dynamic domino and D3L logic styles are presented to serve as low power, high speed, and speed-energy optimized variants of the architecture. When implemented using ST Microelectronics 90 nm 1V cmos technology, the proposed data path leads to a maximum supported clock frequency ranging from 917 MHz to 1.2 GHz with a dynamic power consumption @ 500 MHz ranging from 788 muW to 1.02 mW.

关键词： cmos technology Very large scale integration Throughput Digital signal processing cmos logic circuits Reconfigurable logic Microelectronics Clocks Frequency Energy consumption

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