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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是411-420 订阅

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High-speed low-power FinFET based domino logic

High-speed low-power FinFET based domino logic

引用

Asia and South Pacific Design Automation Conference

作者： Seid Hadi Rasouli Hanpei Koike Kaustav Banerjee Electrical and Computer Engineering University of California Santa Barbara USA Electroinformatics Group Nanoelectronics Research Institute AIST Tsukuba Ibaraki Japan

ISBN: (纸本)9781424427482

This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. The strength of the keeper device is controlled by the differential gate voltage, which guarantees low gate-source voltage at the beginning of the evaluation phase and high gate-source voltage during rest of the time.

关键词： FinFETs logic devices cmos logic circuits cmos technology Energy consumption MOSFETs Low voltage Leakage current Tunneling Subthreshold current

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Nano-magnet based ultra-low power logic design using non-majority gates

Nano-magnet based ultra-low power logic design using non-maj...

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IEEE Conference on Nanotechnology

作者： Charles Augustine Behtash Behin-Aein Kaushik Roy Department of Electrical and Computer Engineering Purdue University USA

ISBN: (纸本)9781424448326

In this paper we explore the intriguing possibility of nano-magnet based logic using non-majority gates. The design approach can offer significant area, delay and energy advantages, compared to a majority-gate based logic design. Our analysis based on NAND-gate based ring-oscillator (RO) shows an improvement of 29% in frequency and 33% in area compared to MQCA based design. Moreover, using the performance metric of millions of operations per second per micro-watt power (P) per micron square area (A) - MOPS/P/A, our RO design with narrow gap cladding H CLOCK enhancement, shows an improvement of 13X compared to an RO in 15 nm cmos technology.

关键词： logic design logic gates cmos technology cmos logic circuits Magnetic anisotropy Perpendicular magnetic anisotropy Couplings Automatic frequency control Magnets Integrated circuit interconnections

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Channel engineering of SOI MOSFETs for RF applications

Channel engineering of SOI MOSFETs for RF applications

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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

作者： C. L. Chen J. M. Knecht J. Kedzierski C. K. Chen P. M. Gouker D-R. Yost P. Healey P. W. Wyatt C. L. Keast Lincoln Laboratory Massachusetts Institute of Technology Lexington MA USA

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard cmos process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.

关键词： MOSFETs Radio frequency Implants FETs Immune system cmos logic circuits logic devices Doping cmos process Transconductance

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A wireless power telemetry with self-calibrated resonant frequency

A wireless power telemetry with self-calibrated resonant fre...

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International Symposium on VLSI Design, Automation and Test

作者： Wei-Jen Huang Chein-Lung Chen Shen-Iuan Liu Graduate Institute of Electronics Engineering & Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9781424427819

A wireless power telemetry with self-calibrated resonant frequency is presented. The proposed calibration scheme adjusts the resonant frequency of inductively secondary coil to match the incident frequency of inductively primary coil. To adjust the resonant frequency of the secondary coil, the received power efficiency is improved. By experimented results, the overall power efficiency with frequency calibration is improved by a factor of 33%, compared with that one without frequency calibration. This wireless power telemetry has been fabricated in a standard 0.35 mum cmos process, and the chip area is 1.536 mm 2 including I/O pads.

关键词： Telemetry Resonant frequency Coils Calibration Voltage Wireless sensor networks Capacitors Coupling circuits Rectifiers cmos logic circuits

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CNT logic knowledge module integrated in digital cmos logic design course

CNT logic knowledge module integrated in digital CMOS logic ...

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IEEE International Conference on Microelectronic Systems Education

作者： Anita Kumari Sanjukta Bhanja Nano Computing Research Group (NCRG) Department of Electrical Engineering University of South Florida USA

We present a knowledge module exposing students to novel Nanodevices and computing issues in the context of cmos Design. This knowledge module has a two-fold objective. First, it generates interest amongst students regarding the fundamental concept of future nano-devices. This will motivate them to enroll in other elective courses related to Nanotechnology, being offered in most EE and CS departments. Further, this module can be used to let students analyze, synthesize and apply their existing knowledge of digital logic design into revolutionary design context with CNT logic. Assessment included the development of rubrics for grading students understanding of key concepts. Survey results and comments indicate that 89% of the students liked the module and demonstration, as well as were enthusiastic and motivated to learn more on nano devices.

关键词： logic design cmos logic circuits Nanotechnology cmos technology Circuit synthesis logic devices Quantum cellular automata Prototypes Quantum dots Single electron transistors

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Research and design of level converter circuit for I/O ports

Research and design of level converter circuit for I/O ports

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Yi-zhong Yang Guang-jun Xie Xuan Zhao School of Electronic Science and Applied Physics Hefei University of Technology Hefei Anhui China

A level converter circuit for I/O ports from 3.3 V LVTTL logic to 1.8 V cmos logic with TSMC 0.18 um cmos process has been designed. Level converter circuit has been integrated in an integrated circuit, which use single supply voltage. A positive feedback circuit similar to the Schmitt flip-flop is adopted to realize the level conversion, which also acts as both a buffer and a waveform shaping role. ESD protection circuit is implemented by the diode and resistor circuit structure traditionally. Signal acquisition circuit use a D flip-flop consisted of the structure of cmos transmission gate. A number of suitable buffers are used to link up them. The circuit has been used in an IC, which works on 250 MHz. The result shows that design satisfies design requirement exactly.

关键词： cmos logic circuits logic design cmos process Flip-flops Process design Voltage Feedback circuits Electrostatic discharge Protection Diodes

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logic LSI technology roadmap for 22 nm and beyond

Logic LSI technology roadmap for 22 nm and beyond

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International Symposium on Physical & Failure Analysis of Integrated circuits

作者： Hiroshi Iwai Frontier Research Canter Tokyo Institute of Technology Yokohama Japan

logic cmos technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008-Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for cmos circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.

关键词： Large scale integration cmos technology cmos logic circuits Delay MOSFETs FETs Energy consumption Lithography Application specific integrated circuits Resists

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A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate cmos with integrated power management

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ...

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IEEE International Conference on Solid-State circuits (ISSCC)

作者： Y. Wang U. Bhattacharya F. Hamzaoglu P. Kolar Y. Ng L. Wei Y. Zhang K. Zhang M. Bohr Intel Hillsboro OR USA

cmos technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role in determining the scaling of SRAM operating voltage (V cc ), frequency and leakage power. We develop a high-performance voltage-scalable SRAM design in 32 nm logic cmos featuring 2nd-generation high-k metal-gate transistors and 4th-generation strained silicon. With the continued transistor performance enhancement and extensive process-circuit co-optimization, the 32 nm SRAM design is able to achieve 2times improvement in density and 15% faster access speed when compared to the 45 nm design at the same voltage. The design supports a broad range of operating voltages to enable dynamic voltage scaling in today's high-performance and low-power applications. The design also features an integrated power management scheme with close-loop array leakage control, floating bitline and wordline driver sleep, resulting in 58% reduction of SRAM leakage consumption.

关键词： Random access memory Energy management cmos technology Dynamic voltage scaling Moore's Law Frequency cmos logic circuits logic devices logic design High K dielectric materials

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A crosstalk minimization technique for sublithographic programmable logic arrays

A crosstalk minimization technique for sublithographic progr...

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IEEE Conference on Nanotechnology

作者： Harika Manem Garrett S. Rose Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

ISBN: (纸本)9781424448326

The emergence of alternative technologies due to continued technology migration into the nanometer regime has led to the design of several novel logic and memory architectures. These architectures, in particular array based architectures built from crossbar structures, aim to achieve higher logic/memory densities with lower power consumption and acceptable delays as compared to present day cmos technology. However crosstalk induced in these nanoscale arrays limits the minimum wire spacing realizable and thereby the logic density that can be achieved. In this work we analyze the crosstalk produced in sublithographic programmable logic array (PLA) architectures and propose an alternative layout scheme that reduces the effects of crosstalk in adjacent wires. The proposed methodology has an interleaved layout scheme with two non-overlapping out-of-phase clocks that prevent neighboring wires from transitioning simultaneously. Results presented in this paper indicate that this scheme provides for better tolerance against crosstalk than other structures proposed for sublithographic PLAs. The effects of different parasitics (i.e. coupling and decoupling capacitances from different parts of the crossbar segment) on the crosstalk induced are also analyzed.

关键词： Programmable logic arrays Crosstalk Minimization cmos logic circuits logic arrays cmos technology Wires logic design Memory architecture Energy consumption

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An on-chip fast readout sparsification for a 256-pixel 3D device

An on-chip fast readout sparsification for a 256-pixel 3D de...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： A. Gabrielli F. Giorgi M. Villa F. Morsani Universita degli Studi di Bologna and INFN-Bologna Italy Universita degli Studi di Pisa and INFN-Pisa Italy

A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is cmos Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process.

关键词： Testing cmos technology Prototypes Application specific integrated circuits logic design Collaboration Silicon cmos logic circuits Foundries logic devices

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