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检索条件"主题词=CMOS Logic Circuits"

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Low dynamic power high performance adder

Low dynamic power high performance adder

引用

International Conference on CAD Systems in Microelectronics (CADSM)

作者： M. Nadi Senejani M. Hossein Ghadiry Department of Computer Engineering Ashtian Branch Islamic Azad University Iran

ISBN: (纸本)9789531841306

This paper presents the design of high performance low dynamic power circuits using a new cmos dynamic logic family, and analyzes power and performance of them, and compares the proposed logic to standard cmos dynamic logic. Results show that the dynamic power reduces at least 26% and the performance improves at least 4.6 times for a 32 bits ripple carry adder in comparison to standard Domino logic. In other hand charge redistribution, limitation of non-inverting only logic and need for output inverter problems of domino logic are completely eliminated.

关键词： cmos logic circuits logic design Adders logic devices Pulse inverters Power dissipation Clocks logic circuits Delay Voltage

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Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems

Subthreshold SCL for ultra-low-power SRAM and low-activity-r...

引用

European Conference on Solid-State circuits (ESSCIRC)

作者： Armin Tajalli Yusuf Leblebici Microelectronic Systems Laboratory (LSM) Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional cmos circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9 T memory cell has been developed to reduce the stand-by (leakage) current to 10 pA/cell while the SRAM array is operating at 2.1 MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer cmos technology nodes.

关键词： Random access memory Digital systems Circuit topology cmos memory circuits Energy consumption cmos technology cmos logic circuits logic circuits Subthreshold current Digital circuits

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Differential Electromagnetic Analysis on AES Cryptographic System

Differential Electromagnetic Analysis on AES Cryptographic S...

引用

Pacific-Asia Conference on Web Mining and Web-based Application, WMWA

作者： Guo-liang Ding Zhi-xiang Li Xiao-long Chang Qiang Zhao Department of Computer Engineering Ordnance Engineering College Shijiazhuang China

To study vulnerability of advanced encryption standard (AES) against side channel attacks(SCAs), first, the article analyzes the cmos logical gate's electric current characteristic under the active status, explains data and electromagnetic emissions correlation of ICs, establishes the electromagnetic information leakage Hamming weight model. Next, aimed at the AES(128 bits) cryptographic system realized by the P89C668 microcomputer, differential electromagnetic analysis (DEMA) algorithm was described, the choosing of attack point and the computational method were analyzed, an attack experiment was processed by DEMA, thereby obtaining secret key of AES(128 bits). After analyzing the experiment result at the instruction level, we find that the most serious leakage of secret information happens in the MOVX instruction which writes the output of S-box into external RAM. The result shows that EM information leakage exists in cmos integrated circuit during work. DEMA is an effective attack on AES. It can provide a basis for implementing protective measures in the cryptographic systems.

关键词： Electromagnetic analysis Cryptography Information analysis cmos logic circuits Current Hamming weight Semiconductor device modeling Electromagnetic modeling Microcomputers Algorithm design and analysis

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Optimum design for ultra wideband Two stage Low Noise Amplifier (UWBLNA)

Optimum design for ultra wideband Two stage Low Noise Amplif...

引用

National Conference on Radio Science (NSRC)

作者： Mohamed R. M. Rizk Mohamed Nasar Alaa Hafez Faculty of Engineering Alexandria University Alexandria Egypt Faculty of Air Defense Alexandria Egypt

A Two stage, common gate in cascade with common source, ultra wideband low noise amplifier (UWBLNA) is analyzed and optimized for 1 to 16 GHz full band application. The common gate first stage is adopted for wideband input impedance matching. The common source stage provides a wideband gain. Two structures of (UWBLNA) are studied and optimized in order to achieve a maximum gain over a wide band of frequencies while noise figure (N.F) remains unchanged. Simulation results carried out sever improvement for the gain over a wideband of frequencies. The average optimized gain for the first structure is 21.15 dB with average improvement of 15.5 %. For the second structure the optimized gain is 15.3 dB with average improvement of 18.4 %. The optimized structures are compared and show a good performance over a wideband of frequencies.

关键词： Ultra wideband technology Broadband amplifiers Low-noise amplifiers Leakage current Circuit testing cmos logic circuits Electronic equipment testing Combinational circuits Application specific integrated circuits Circuit faults

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Design of nanometer MOS Current Mode logic: From very high-speed down to ultra-low power

Design of nanometer MOS Current Mode Logic: From very high-s...

引用

International Conference on Microelectronics, ICM

作者： Massimo Alioto Berkeley Wireless Research Center Berkeley CA USA

In the last years, MOS Current-Mode logic (MCML) circuits have become very popular in a wide range of applications, from high-accuracy mixed-signal circuits to very high-speed circuits, and very recently for ultra-low power circuits. In MCML circuits, desirable features come at the cost of static power consumption, hence power-aware design techniques are needed. At the same time, issues related to the high complexity of current circuits (e.g., design automation) and nanometer technologies (e.g., variability) must be explicitly taken into account in real designs. In this tutorial, a survey of fresh ideas and recent techniques to design MCML circuits is presented. Concepts are introduced in a design perspective and cover multiple levels of abstraction, ranging from transistor to system. A comparison with cmos logic is presented to identify the applications where MCML exhibit better features. Models for MCML circuits in nanometer cmos technologies are presented and then used to derive power-aware design guidelines and criteria for a wide variety of applications. Since commercial CAD tools do not explicitly support differential logic styles, issues related to the CADbased automated design of complex circuits are discussed, and recently proposed solutions are reviewed. Guidelines are developed to design standard cells and perform automated synthesis and place & route with standard tools. Design criteria for area-power efficient differential routing are also given. Variability issues are explicitly dealt with and considered from the beginning, rather than as an afterthought. System-level biasing schemes to dynamically control the power-speed tradeoff and compensate variations are discussed for a wide range of applications, from very high speed to ultra-low power. MCML gates are also shown to be better suited for ultra-low power operation (e.g., to implement the digital processing unit in wireless sensor nodes), compared to cmos logic. Design issues arising in the ultralow

关键词： logic design cmos logic circuits cmos technology Voltage logic circuits Energy consumption Design automation Guidelines Standards development Costs

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ICECS 2009 keyword index

ICECS 2009 keyword index

引用

IEEE International Conference on Electronics, circuits and Systems (ICECS)

Presents an index of the articles published in the conference.

关键词： cmos analog integrated circuits cmos digital integrated circuits cmos logic circuits cmos process Adaptive filters Digital filters Filtering theory Algorithm design and analysis Feedback circuits Clocks

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Radiation damage characterization of digital integrated circuits

Radiation damage characterization of digital integrated circ...

引用

Latin American Test Workshop, LATW

作者： Santiago Sondon Pablo Mandolesi Pedro Julian Felix Palumbo Martin Alurralde Alberto Filevich GISEE Universidad Nacional del Sur Bahia Blanca Argentina Grupo Energía Solar-CAC Comisión Nacional de Energía Atómica Buenos Aires Argentina

A set of gates and registers was fabricated on a submicron cmos process using radiation hardening by design techniques. The circuits were irradiated in a tandem accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.

关键词： Digital integrated circuits Registers cmos process Radiation hardening Proton accelerators Electric variables measurement Integrated circuit measurements Integrated circuit noise logic gates cmos logic circuits

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NBTI-aware technique for transistor sizing of high-performance cmos gates

NBTI-aware technique for transistor sizing of high-performan...

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Latin American Test Workshop, LATW

作者： Mauricio B. da Silva Vinicius V. A. Camargo Lucas Brusamarello Gilson I. Wirth Roberto da Silva Universidade Federal do Rio Grande do Sul Porto Alegre Brazil

NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of cmos circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance cmos gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32 nm technology using our methodology presents 6% delay reduction at year 3 compared to a traditional sizing methodology, both using the same area. For a NAND gate we achieved a delay improvement up to 11%. The methodology here proposed can be extended to other cmos logic gates, including complex gates.

关键词： cmos technology Delay Niobium compounds Titanium compounds cmos logic circuits MOSFETs Timing Degradation Inverters logic gates

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Static and dynamic test power reduction in scan-based testing

Static and dynamic test power reduction in scan-based testin...

引用

International Symposium on VLSI Design, Automation and Test

作者： Sying-Jyan Wang Shun-Jie Huang Katherine Shu-Min Li Department of Computer Science and Engineering National Chung Hsing University Taichung Taiwan Department of Computer Science and Engineering National Sun Yat-Sen University Kaohsiung Taiwan

ISBN: (纸本)9781424427819

Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process, and this vector can also be used to reduce dynamic power. However, the reverse is not always true. A heuristic algorithm is presented to find such vectors. The proposed method is simulated by SPICE with BPTM 22 nm transistor model, and the results show that on the average 15% total power reduction is achievable by the proposed method.

关键词： Leakage current Energy consumption Circuit testing cmos technology cmos logic circuits Computer science Power engineering and energy SPICE Power dissipation Transistors

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An 8.9mW 25Gb/s inductorless 1:4 DEMUX in 90nm cmos

An 8.9mW 25Gb/s inductorless 1:4 DEMUX in 90nm CMOS

引用

International SoC Design Conference, ISOCC

作者： Takayuki Sekiguchi Shuhei Amakawa Noboru Ishihara Kazuya Masu Integrated Research Institute Tokyo Institute of Technology Yokohama Japan

ISBN: (纸本)9781424450343;9781424450350

A low-power inductorless 1:4 DEMUX in 90 nm cmos is presented. It is capable of operating at 25 Gb/s with a power supply voltage of 1.05 V, and the power consumption is 8.9 mW. Its area is 29 × 40 ¿m 2 . The DEMUX consists primarily of latches in differential pseudo-NMOS logic style. This logic style has a near-rail-to-rail logic swing and is much more scalable under low V dd than the current-mode logic, commonly used for high-performance SerDes. It is also compatible with the conventional cmos logic, and direct connection with cmos logic gates is possible without logic level conversion. The low power, small footprint, and reasonable speed could be beneficial for chip-to-chip communication within a multi-chip module.

关键词： cmos logic circuits Clocks Voltage Integrated circuit interconnections Frequency conversion cmos technology Packaging Latches MOSFETs Paper technology

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