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检索条件"主题词=CMOS Logic Circuits"

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A novel approach of And-Or-Inverter (AOI) gate design for QCA

A novel approach of And-Or-Inverter (AOI) gate design for QC...

引用

International Conference on Computers and Devices for Communication (CODEC)

作者： Kunal Das Debashis De Department of Computer Science & Engineering West Bengal University of Technology Kolkata India

Quantum dot cellular automata (QCA) define the nano structure of a basic computer. It is used as an alternative for designing high-speed computer over cmos technology. The basic logic in QCA is the logic state that does not measure with voltage level; rather it measures the polarity of electrons in cell. The Majority Voter (MV) is first introduced to design the logic circuits, but only using MV, designing complex logic circuit became inefficient. Many proposals had been made for designing QCA logic gate. In this paper we focus on Novel nanostructure, reduced size and efficient design of ¿And-Or-Inverter¿ (AOI) and also present comparison with previously reported AOI gate. We design New AOI gate using a combination of Nand-Nor-Inverter (NNI) and MV. Simulation result shows almost 54% reductions in size of AOI gate and improving gate delay due to less complexity on compare to early report. We analyze QCA defect on proposed AOI gate and describe its permissible defect tolerance. We also describe NNI with its QCA nano structure.

关键词： Quantum cellular automata Quantum computing cmos technology cmos logic circuits logic circuits Quantum dots Voltage measurement Electrons Proposals logic gates

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Implementation and prototyping of a complex multi-project system-on-a-chip

Implementation and prototyping of a complex multi-project sy...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Chun-Ming Huang Chien-Ming Wu Chih-Chyau Yang Wei-De Chien Shih-Lun Chen Chi-Shi Chen Jiann-Jenn Wang Chin-Long Wey National Chip Implementation Center Hsinchu Taiwan Department of Electrical Engineering National Central University Jhong Li Taiwan

ISBN: (纸本)9781424438273

A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The total silicon area is about 37.97 mm 2 in the TSMC 0.13 um cmos generic logic process technology. Compared with the total chip area 129.39 mm 2 by implementing these projects separately, the results show that there are 91.42 mm 2 silicon areas reduced by the MP-SoC platform. In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented. A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.

关键词： Prototypes System-on-a-chip Silicon Software prototyping Hardware Costs cmos process cmos logic circuits cmos technology Virtual prototyping

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Benefits of decomposing wide cmos transistors into minimum-size gates

Benefits of decomposing wide CMOS transistors into minimum-s...

引用

Norchip

作者： Hans Kristian Otnes Berge Snorre Aunet Department of Informatics University of Oslo Norway

In this paper we show how decomposition of a wide cmos transistor into a multi-finger FET with gates of minimum size can be beneficial for the reduction of delay and power-delay products in logic gates. This design possibility, which we call a minimum-split transistor (MST), seems to be largely overlooked in the literature. In a 90 nm cmos process we compare the design to wide transistors. By exploiting the narrow-width effect, reduced parasitic capacitances from a shorter active channel and increased gate-drain spacing, we achieve up to 75-85% higher operation speed at a similar or reduced power consumption. The worst-case timing delay is reduced by 35-40% along with the nominal values. The design technique is considered valuable, in particular for critical time paths. The paper takes the perspective of subthreshold logic design at 200 mV, but the technique is also useful above threshold. A statistical experiment also investigates how V th variation in MSTs changes with the number of parallell gates.

关键词： Delay cmos logic circuits Timing logic design Informatics cmos process Energy consumption Ring oscillators Implants Capacitance

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Handshaking quasi-adiabatic logic

Handshaking quasi-adiabatic logic

引用

Midwest Symposium on circuits and Systems (MWSCAS)

作者： Meng-Chou Chang Chia-Chang Tsai Department of Electronic Engineering National Changhua University of Education Changhua Taiwan

ISBN: (纸本)9781424444793;9781424444809

This paper proposes a novel handshaking quasi-adiabatic logic (HQAL) circuit, which combines the advantages of adiabatic logics with those of asynchronous circuits. A HQAL circuit is composed of adiabatic logic blocks and the handshake control chain (HCC). The power of the adiabatic logic blocks in HQAL is controlled and supplied by the HCC, and the logic blocks in HQAL become active only when performing useful computations. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the cmos implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz.

关键词： logic circuits cmos logic circuits Power supplies logic design Power dissipation Pipeline processing Switches Voltage Asynchronous circuits Clocks

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Technology Projection Using Simple Compact Models

Technology Projection Using Simple Compact Models

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： H.-S. Philip Wong Lan Wei Saeroonter Oh Albert Lin Jie Deng Soogine Chong Kerem Akarvardar Department of Electrical Engineering and Center of Integrated Systems University of Stanford Stanford CA USA

We review recent efforts to capture the device nonidealities for circuit-level technology projection for Si cmos. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.

关键词： Parasitic capacitance Semiconductor device modeling cmos technology MOSFETs III-V semiconductor materials cmos logic circuits Switching circuits FETs Carbon nanotubes Nanoscale devices

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Quasi-adiabatic 2×2 Barrel Shifter

Quasi-adiabatic 2×2 Barrel Shifter

引用

International Conference on Industrial and Information Systems, ICIIS

作者： Prasad D Khandekar Shaila Subbaraman Venkat Raman Vinjamoori E&TC Vishwakarma Institute of Information Technology Pune India Walchand College of Engineering Sangli India International Institute of Information Technology Pune Maharashtra IN

Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional cmos circuits include reducing the supply voltages, node capacitances, and switching frequencies. Energy-recovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. Such circuits achieve low energy dissipation by restricting current to flow across devices with very low voltage drop and by recycling the energy stored on their capacitors. This paper analyzes the performance of Pass Transistor Adiabatic logic (PAL) against that of static cmos. A standard 2X2 Barrel Shifter is used as the benchmark circuit for comparison due to its modular design. The analysis is carried out in cadence design environment using 180nm technology using cell based design approach. The simulation is done at various operating voltages, frequencies, and load capacitances for each circuit family and technological node.

关键词： Energy dissipation Very large scale integration Capacitance Low power electronics Switching frequency Low voltage Recycling Switched capacitor circuits Performance analysis cmos logic circuits

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Static ultra low voltage cmos logic

Static ultra low voltage CMOS logic

引用

Norchip

作者： Y. Berg Nanoelectronics Department of Informatics University of Oslo Oslo Norway

In this paper we examine a quasi static and a static ultra low-voltage precharge cmos logic. The static ultra low-voltage logic can be used to design high speed and energy efficient cmos circuits. Using the proposed circuit technique the static current consumption can controlled and the logic style is suitable for large logic depth, i.e. serial adders. The delay of a static ultra low-voltage gate can be reduced to less than 10% compared to a static complementary gate.

关键词： Low voltage cmos logic circuits Energy consumption Threshold voltage Inverters logic circuits Leakage current cmos technology Nanoelectronics Informatics

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Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n

Performance Evaluation and ASIC Design of LDPC Decoder for I...

引用

Consumer Communications and Networking Conference, CCNC IEEE

作者： W. A. Syafei R. Yohena H. Shimajiri T. Yoshida M. Kurosaki Y. Nagao B. Sai H. Ochi Department of Computer Science and Electronics Kyushu Institute of Technology Fukuoka Japan Department of Information Engineering University of Ryukyus Nishihara Okinawa Japan Frontier Okinawa 21 Company Limited Naha Okinawa Japan Radrix Company Limited Japan

This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. logic synthesis is succesfully done on 0.13 mum cmos technology with low-power standard cell library.

关键词： Application specific integrated circuits Parity check codes Decoding cmos technology Circuit simulation Convolutional codes cmos logic circuits Integrated circuit synthesis Integrated circuit technology Libraries

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Combinational logic design in Synthetic Biology

Combinational logic design in Synthetic Biology

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Douglas Densmore J. Christopher Anderson Department of Electrical Engineering and Computer Sciences University of California Berkeley Berkeley CA USA Department of Bioengineering University of California Berkeley Berkeley CA USA

ISBN: (纸本)9781424438273

Combinational logic circuits are a fundamental building block in today's digital electronics. Combinational logic representations are highly amenable to various levels of abstraction, and manipulation is naturally performed via Boolean algebraic expressions. These properties have allowed automatic VLSI synthesis and analysis capabilities to reach a high level of maturity. In the growing field of Synthetic Biology, devices are emerging which are being classified as ldquocombinational logicrdquo. These devices can be constructed using standardized design practices which pave the way to more advanced analysis and construction techniques. However there exist a number of barriers to the application of VLSI design techniques to biological systems. We describe two key barriers and begin the process of examining how difficult they will be to overcome.

关键词： logic design Synthetic biology logic devices Switches Very large scale integration cmos logic circuits logic gates Chemical technology Biology computing Biological systems

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Design and analysis of online testability of reversible sequential circuits

Design and analysis of online testability of reversible sequ...

引用

International Conference on Computer and Information Technology (ICCIT)

作者： Moshaddek Hasan A.K.M. Tauhidul Islam Ahsan Raja Chowdhury Dept. of Computer Science and Engineering University of Dhaka Dhaka Bangladesh

Reversible logic plays an important role in the synthesis of circuits having application in quantum computing, low power cmos design and nanotechnology-based system. In this paper, we have proposed the online testability of reversible sequential circuits, which is first ever proposed in literature. On the way to propose the online testability of reversible sequential circuits, we have proposed an improved rail-check circuit that significantly improves the performance of the overall circuit in terms of gate cost and garbage cost parameters. We have also used our improved and efficient rail-check circuit to realize the testability of different benchmark circuits.

关键词： Circuit testing Sequential analysis Sequential circuits cmos logic circuits Quantum computing Costs logic design Circuit synthesis Computer applications Benchmark testing

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