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检索条件"主题词=CMOS Logic Circuits"

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A stackable cross point Phase Change Memory

A stackable cross point Phase Change Memory

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International Electron Devices Meeting (IEDM)

作者： DerChang Kau Stephen Tang Ilya V. Karpov Rick Dodge Brett Klehn Johannes A. Kalb Jonathan Strand Aleshandre Diaz Nelson Leung Jack Wu Sean Lee Tim Langtry Kuo-wei Chang Christina Papagianni Jinwook Lee Jeremy Hirst Swetha Erra Eddie Flores Nick Righos Hernan Castro Gianpaolo Spadini Technology and Manufacturing Group Intel Corporation Santa Clara CA USA Research and Development Technology Development Numonyx San Jose CA USA

A novel scalable and stackable nonvolatile memory technology suitable for building fast and dense memory devices is discussed. The memory cell is built by layering a storage element and a selector. The storage element is a Phase Change Memory (PCM) cell and the selector is an Ovonic Threshold Switch (OTS). The vertically integrated memory cell of one PCM and one OTS (PCMS) is embedded in a true cross point array. Arrays are stacked on top of cmos circuits for decoding, sensing and logic functions. A RESET speed of 9 nsec and endurance of 10 6 cycles are achieved. One volt of dynamic range delineating SET vs. RESET is also demonstrated.

关键词： Phase change memory Phase change materials Switches Nonvolatile memory logic arrays cmos logic circuits cmos memory circuits Decoding logic functions Dynamic range

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Reliability of NAND-2 cmos gates from threshold voltage variations

Reliability of NAND-2 CMOS gates from threshold voltage vari...

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International Conference on Innovations in Information Technology

作者： Walid Ibrahim Valeriu Beiu College of Information Technology United Arab Emirates University Al-Ain UAE Systems and Computer Engineering Department Carleton University Ottawa Canada School of Intelligent Systems University of Ulster Magee UK

ISBN: (纸本)9781424456987

The high-level approach for estimating circuit reliability tends to consider the probability of failure of a logic gate as a constant, and work towards the higher levels. With scaling, such gate-centric approaches become highly inaccurate, as both transistors and input vectors drastically affect the probability of failure of the logic gates. This paper will present a transistor-level gate failure analysis starting from threshold voltage variations. We will briefly review the state-of-the-art, and rely upon freshly reported results for threshold voltage variations. These will be used to estimate the probabilities of failure of a classical NAND-2 cmos gate for (a few) different technologies, voltages, and input vectors. They will also reveal huge differences between the highest and the lowest probabilities of failure, and will show how strongly these are affected by the supply voltage.

关键词： Threshold voltage MOSFETs Fluctuations Doping Analytical models cmos logic circuits logic gates Microscopy Computational modeling Electrons

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On chip LC resonator circuit using an active inductor for adiabatic logic

On chip LC resonator circuit using an active inductor for ad...

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Midwest Symposium on circuits and Systems (MWSCAS)

作者： Yasuhiro Takahashi Nazrul Anuar Shun-ya Nagano Toshikazu Sekine Michio Yokoyama Department of Electrical and Electronic Engineering Gifu University Gifu Japan Department of Bio-system Engineering Yamagata University Yonezawa Japan

In this paper, we propose a LC resonator circuit using Hara's active inductor for adiabatic logic. The proposed circuit consists of four MOS-transistors Colpitts oscillator and an active inductor. This circuit require no inductor and can be produced two-phase sinusoidal clocking. From the simulation results, we show that the proposed circuit was operated as a 10 MHz, 3 V peak-to-peak LC resonant oscillator.

关键词： Active inductors logic circuits Resonance cmos logic circuits Driver circuits Oscillators Inverters MOSFETs Switches Pulse generation

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Achieving sub-adiabatic energy dissipation by varying VBS

Achieving sub-adiabatic energy dissipation by varying VBS

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International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON

作者： Prasad D. Khandekar Shaila Subbaraman Vishwakarma Institute of Information Technology Pune India Walchand College of Engineering and Technology Sangli India

This paper proposes a new method of reducing the energy dissipation below that of quasi-adiabatic circuit. Adiabatic logic style is proving to be an attractive solution for low power digital design. Many researchers have introduced different adiabatic logic styles in last few years and proved that these are better than cmos as far as power dissipation is concerned. In this paper, we present control circuits for sub-adiabatic energy dissipation and show that the energy dissipation of the quasi-adiabatic circuit can be further reduced if we control bulk-to-source voltage, V BS appropriately. All the inverter circuits are designed using 180 nm technology in Cadence design environment.

关键词： Energy dissipation Power dissipation Threshold voltage Inverters Switches Power supplies Capacitors MOS devices logic circuits cmos logic circuits

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Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband(IR-UWB) transceivers

Transmitter equalization for multipath interference cancella...

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International Symposium on VLSI Design, Automation and Test

作者： Changhui Hu Steven Redfield Huaping Liu Rahul Khanna Jay Nejedlo Patrick Chiang School of Electrical Engineering and Computer Science Oregon State University Corvallis OR USA

ISBN: (纸本)9781424427819

This paper presents a novel cmos 2-tap equalizer for combating multipath interference in impulse radio, ultra-wideband (IR-UWB) transceiver systems. The equalizer is composed of pulse width control, pulse tap delay control, pulse sign inversion, and current mode logic (CML) summation for data transmission. SpectreRF post-layout simulation in a 90-nm cmos technology shows that the transceiver operates up to a 2 Gbps data rate by removing the 1 st and 2 nd multipath reflections, illustrating significant signal-to-noise (SNR) improvement when compared with a conventional transmitter.

关键词： Radio transmitters Interference cancellation Transceivers Space vector pulse width modulation Equalizers cmos technology Ultra wideband technology Delay cmos logic circuits Data communication

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Computing bounds on dynamic power using fast zero-delay logic simulation

Computing bounds on dynamic power using fast zero-delay logi...

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Southeastern Symposium on System Theory

作者： Jins D. Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Aubum University Auburn AL USA

To consider process variation, we model gates with given lower and upper bounds on delays. For given input vectors, we first find logic transitions using zero-delay simulation. Our algorithms then determine the ambiguity (transient) interval, and maximum and minimum numbers for possible transitions. Computing these for all gates requires a linear-time analysis of each vector-pair. Weighting with node capacitances estimates lower and upper bounds on dynamic power. Results compare favorably with power analysis using Monte Carlo simulation, which requires significantly more computing resources. Bounded variations for node capacitances and leakage, not used in this work, are suggested for future investigation.

关键词： Computational modeling Delay estimation Energy consumption Capacitance Analytical models Power generation cmos logic circuits Upper bound Circuit simulation Monte Carlo methods

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A Look-Up-Table Based Differential logic to counteract DPA attacks

A Look-Up-Table Based Differential Logic to counteract DPA a...

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International Conference on ASIC

作者： Daheng Yue Yan Sun Minxuan Zhang Shaoqing Li Yutong Dai School of Computer National University of Defense Technology Changsha China Computer School of National University of Defense Technology Changsha China

Dual-rail precharge (DRP) logic styles, such as wave dynamic differential logic (WDDL), have been proposed as a countermeasure against differential power analysis (DPA) for years. Because of the constant transition rate, the correlation between power consumption and signal values is significantly reduced. However, leakage still occurs in these logic styles caused by the difference of signal delay time. In this paper, a novel look-up-table (LUT) based differential logic (LBDL) is presented. The transition time of LBDL gates are independent of input values, hence the power consumption of LBDL is constant though the signals have different delays. Experimental results indicate that LBDL eliminates most of the leakage, while the performance and area costs are similar to WDDL.

关键词： Energy consumption logic circuits cmos logic circuits logic gates Delay effects Table lookup Information security Cryptography Sun Algorithm design and analysis

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High voltage SOI P-channel field MOSFET structures

High voltage SOI P-channel field MOSFET structures

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： David Hongfei Lu Tomonori Mizushima Hitoshi Sumida Masaru Saito Haruo Nakazawa Electron Device Laboratory Fuji Electric Device Technology Company Limited Matsumoto Japan

We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (~20 V per um of drift length) for both off- and on- state breakdown voltage close to 300 V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum overhead area by source-centered single trench structure in which the trench sidewall grounded.

关键词： Voltage MOSFET circuits Silicon on insulator technology Isolation technology Thick films Integrated circuit technology cmos logic circuits Plasma displays logic devices Electron devices

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High speed I/O and thermal effect characterization of 3D stacked ICs

High speed I/O and thermal effect characterization of 3D sta...

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IEEE International Conference on 3D System Integration, 3DIC

作者： Moishe Groger Shadi M. Harb Devin Morris William R. Eisenstadt Sudeep Puligundla Department of Electrical & Computer Engineering University of Florida Gainesville FL USA Intel Corporation Hillsboro OR USA

This work focuses on characterizing the performance of the 3D TSVs under high speed transient simulation, which could potentially evaluate and verify the electrical models for these vertical connections. A gunning transceiver logic (GTL) I/O on-chip test IC and a CML/thermal test IC has been designed and sent for fabrication using the 3D FDSOI cmos technology. The GTL I/O circuits are used to inject different data patterns at different frequencies across different tiers. A control MUX with tri-state buffers and control logic can be used to switch between different I/O GTL drivers at different tiers. The GTL I/O test IC is dedicated to measure the NEXT/FEXT crosstalk between vertical connections by firing high speed signals from different tiers. The data-dependent-jitter (DDJ) will be characterized by observing the eye diagram for a random and different data patterns. CML I/O circuits were designed to characterize high speed differential transmission, especially, the performance of high current buffers in the three tiered-system implementation. Differential signals were used to test the performance of through-silicon vias (TSV) and interconnect as the signals transmit from IC tier-to-tier. In addition, temperature sensors were integrated in order to model the 3D thermal performance as affected by the I/O drivers.

关键词： Circuit testing Integrated circuit testing logic testing cmos logic circuits cmos integrated circuits cmos technology Switches Through-silicon vias Circuit simulation Semiconductor device modeling

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Analysis and comparison of high performance cmos adiabatic drivers

Analysis and comparison of high performance CMOS adiabatic d...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Jose C. Garcia Juan A. Montiel-Nelson Saeid Nooshabadi Institute of Applied Microelectronics University of Las Palmas Las Palmas Spain Department of Information and Communication Gwangju Institute of Science and Technology South Korea

ISBN: (纸本)9781424438273

This paper presents the design and comparative evaluation of four low energy cmos adiabatic drivers; ib-drive using a dual-rail structure with complementary input and output; scal-driver using a single input stage based on a single transistor driving a pair of cross-coupled cmos inverters; ob-driver using an output stage with two inverters driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells; ee-driver using an output stage with two bootstrap capacitors driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13 mum cmos 1.0 V technology, ib-driver performs better than the other adiabatic circuits, in terms of the energy-delay product by up to 68%.

关键词： Performance analysis cmos logic circuits Switches Driver circuits Voltage Switching circuits logic design Pulse inverters cmos technology Switched capacitor circuits

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