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检索条件"主题词=CMOS Logic Circuits"

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Correlation Electromagnetic Analysis for Cryptographic Device

Correlation Electromagnetic Analysis for Cryptographic Devic...

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Pacific-Asia Conference on circuits, Communications and Systems, PACCS

作者： Guo Liang Ding Jie Chu Liang Yuan Qiang Zhao Department of Computer Engineering Ordnance Engineering College Shijiazhuang China

The article analyzes the cmos logical gate's electric current characteristic under the active status, establishes the electromagnetic information leakage hamming distance model in registers level. Aimed at the data encryption standard (DES) cryptographic system realized by the P89C668 microcomputer, Correlation Electromagnetic Analysis (CEMA) algorithm was described, the choosing of attack point D and the computational method were analyzed, an attack experiment was processed by CEMA, thereby obtaining 48-bits sub-key of the 16th round of DES. The result shows that EM information leakage exists in cmos integrated circuit during work, XOR operation in each round of DES is an attack point. It can provide a basis for implementing protective measures in the cryptographic systems.

关键词： Electromagnetic analysis Cryptography Information analysis cmos logic circuits Current Hamming distance Semiconductor device modeling Electromagnetic modeling Registers Microcomputers

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Low-voltage process-adaptive logic and memory arrays for ultralow-power sensor nodes

Low-voltage process-adaptive logic and memory arrays for ult...

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IEEE SENSORS

作者： Kaushik Roy Jaydeep Kulkarni Myeong Hwang Purdue University West Lafayette IN USA

We propose process variation tolerant circuit techniques for robust digital subthreshold logic and memory for ultralow power sensor nodes. Based on the concepts developed in this paper, we present an 8×8 process-tolerant FIR filter, working in both superthreshold and subthreshold regions featuring adaptive ß-ratio modulation and integrated level converters. Ultra-dynamic voltage scaling (UVDS) enables the filter operation at 85 mV consuming 40 nW. For memory applications, we propose Schmitt Trigger based SRAM bitcell exhibiting built-in process variation tolerance. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 ¿m cmos technology.

关键词： Sensor arrays logic arrays Virtual manufacturing Robustness cmos logic circuits logic circuits Dynamic voltage scaling cmos technology MOS devices Finite impulse response filter

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Bootstrapped Adiabatic Complementary Pass-Transistor logic Driver Circuit for Large Capacitive Load and Low-energy Applications

Bootstrapped Adiabatic Complementary Pass-Transistor Logic D...

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Euromicro Symposium on Digital System Design

作者： José Carlos Garcia-Montesdeoca Juan A. Montiel-Nelson Saeid Nooshabadi J. Sosa Héctor Navarro Institute for Applied Microelectronics University of Las Palmas Spain Department of Information and Communication Gwangju Institute of Science and Technology South Korea

This paper presents the design of an adiabatic/bootstrapped cmos driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65 nm cmos IV technology, under the large capacitive loading condition (16pF), xb-ad performs better than the reference adiabatic circuit (cpl-ad) in terms of active area (64%), and energy-delay product (39%). Moreover, xb-ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl-ad.

关键词： logic circuits Driver circuits cmos logic circuits Clocks Delay cmos technology Capacitors Voltage Energy consumption Energy efficiency

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Transient analysis of MEMS cantilever based binary inverter and design of a ring oscillator

Transient analysis of MEMS cantilever based binary inverter ...

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International Conference on Computers and Devices for Communication (CODEC)

作者： Subha Chakraborty Ashesh Ray Chaudhuri T. K. Bhattacharyya Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur India

This paper presents analysis of transient response of a MEMS cantilever based binary logic inverter. The design of the cantilever structures have been optimized with finite element method based simulation in Coventorware platform and system level simulation in Saber Architect platform. Analysis of the turn-on and turn-off time for the inverter has been attempted with analytical and numerical techniques. A ring oscillator has been designed with the inverter to estimate the propagation delay through the device.

关键词： Transient analysis Micromechanical devices Ring oscillators Pulse inverters Structural beams Electrodes Propagation delay cmos logic circuits Transient response Design optimization

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Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in cmos 90nm technologies

Measuring the effectiveness of symmetric and asymmetric tran...

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Latin American Test Workshop, LATW

作者： Thiago Assis Fernanda Lima Kastensmidt Gilson Wirth Ricardo Reis Universidade Federal do Rio Grande do Sul Brazil

Transistor sizing is a well-known technique to reduce Single Event Transients in nanometer technologies. In this work, the transistor sizing technique is evaluated at a 90 nm 3D device model for SET robustness. Mix-mode simulations at TCAD were performed in three basic logic gates of the ST 90 nm standard cell library. Results indicate that the transistor sizing can be more or less efficient to reduce SET according to the collected charge. For alpha particles, the technique can enhance the reliability for high transistor width sizes, while for high-energy particles the technique can increase the transient pulse amplitude and duration making SET effect even worse.

关键词： cmos technology Size measurement Semiconductor device modeling Robustness logic gates cmos logic circuits logic devices Libraries Alpha particles Space vector pulse width modulation

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Design and implementation of 0.8-V Active RC polyphase filter using 0.18-µm cmos inverters with resistive level shifter

Design and implementation of 0.8-V Active RC polyphase filte...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Kazuki Yazawa Hiroshi Tanimoto Kitami Institute of Technology Kitami Hokkaido Japan

ISBN: (纸本)9781424438273

A cmos inverter based amplifier operable down to 0.8 V of power supply has been proposed. The cmos inverter amplifier has a level shifter circuit at its input to effectively reduce its threshold voltages. The level shift is realized by feeding an input signal via a resistive voltage divider which is connected between VDD and GND. The proposed amplifiers are used to construct a three-stage active RC polyphase filter with 0.3 to 3 MHz passband. The active RC polyphase filter was fabricated in 0.18 mum cmos technology, and measured results show that the proposed amplifier successfully operates from 0.8 V supply voltage.

关键词： Active filters Inverters Threshold voltage cmos technology Resistors Power supplies Capacitors Power amplifiers cmos logic circuits Leakage current

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MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues 09

MTJ-based nonvolatile logic-in-memory circuit, future prospe...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Shoun Matsunaga Jun Hayakawa Shoji Ikeda Katsuya Miura Tetsuo Endoh Hideo Ohno Takahiro Hanyu Laboratory of Brainware Systems Research Institute of Electrical Communication (RIEC) University of Tohoku Sendai Japan Hitachi Advanced Research Laboratory Tokyo Japan Laboratory of Nanoelectronics and Spintronics RIEC University of Tohoku Sendai Japan Center of Interdisciplinary Research University of Tohoku Sendai Japan

ISBN: (纸本)9783981080155

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (cmos)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 mum cmos/MTJ process, and its future prospects and issues are discussed.

关键词： Magnetic tunneling Nonvolatile memory logic circuits Memory architecture Integrated circuit interconnections Delay MOSFETs Scalability Concrete cmos logic circuits

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A 2.5 V 0.13 μm cmos amplifier for a high-temperature sensor system

A 2.5 V 0.13 μm CMOS amplifier for a high-temperature senso...

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Annual IEEE Northeast Workshop on circuits and Systems (NEWCAS)

作者： Nima Sadeghi Shahriar Mirabbasi Chad P. J. Bennington Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada Department of Chemical and Biological Engineering University of British Columbia Vancouver BC Canada

A high-temperature amplifier, designed and simulated in a 0.13 mum cmos process, is presented. The amplifier is intended to operate in a wood chip digester used for pulp manufacture in which the ambient temperature can be as high as 180degC. Since the foundry provided modeled are valid up to 125degC, the amplifier along with its bias circuitry is simulated up to 125degC by considering a reasonable margin for the gain and gain bandwidth when temperature increases beyond 125degC. At 125degC, the amplifier has a DC gain of 69 dB, phase margin of 86deg and unity gain bandwidth of 4.13 MHz, while consuming 0.62 mW (excluding the bias circuitry) from a 2.5 V supply.

关键词： Sensor systems Temperature sensors cmos process cmos logic circuits cmos technology Batteries Pulp manufacturing Circuit simulation Bandwidth Aerospace industry

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Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

Comparison of alpha-particle and neutron-induced combination...

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Annual International Symposium on Reliability Physics

作者： B. Gill N. Seifert V. Zia Intel Corporation Hillsboro OR USA

We report on particle induced upset rates of combinational and sequential logic. A novel test chip has been designed in a 32 nm process to study the effects of single event transients (SET) and to verify the accuracy of our simulation models. The test chip has been tested under neutron and alpha particle radiation. Our measured data verify simulation-based projections that while static logic at the 32 nm technology node is sensitive to both alpha particle and neutron radiation, it is not a dominant contributor at the chip-level.

关键词： Error analysis Voltage Circuit simulation Neutrons logic devices cmos logic circuits Single event upset Testing Alpha particles Clocks

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Redefining cmos logic style for subthreshold operation

Redefining CMOS logic style for subthreshold operation

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Ph.D. Research in Microelectronics and Electronics (PRIME)

作者： Sreehari Veeramachaneni M.B. Srinivas Centre of VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad India Department Electronics and Communication Engineering Birla Institute of Technology and Science Hyderabad India

Sub-threshold design of cmos logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional cmos logic style may not function properly at 65 nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new cmos logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65 nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.

关键词： cmos logic circuits logic devices Leakage current Degradation logic design cmos technology MOS devices logic circuits Stacking Voltage

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