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Radix-4³ based two-dimensional FFT architecture with efficient data reordering scheme

IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第2期13卷 78-86页

作者： Kala, S. Mathew, Jimson Jose, Babita R. Nalesh, S. Cochin Univ Sci & Technol Sch Engn Kochi 22 Kerala India Indian Inst Technol Patna Dept Comp Sci & Engn Patna Bihar India Cochin Univ Sci & Technol Dept Elect Kochi 22 Kerala India

Multi-dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 x 64 point 2D FFT architecture based on radix-43 algorithm using a parallel unrolled radix-4(3) FFT as the basic block. Our radix-4(3) architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Proposed architecture produces reordered output of both 64-point one dimensional (1D) FFT and 64 x 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm cmos technology with clock frequency of 500 MHz and area of 0.841 mm(2). The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 x 64 point FFT is 8.19 mu s. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state-of-art implementation. Proposed architecture has also been implemented in Virtex-7 FPGA which gives comparable area.

关键词： application specific integrated circuits parallel architectures field programmable gate arrays computational complexity discrete Fourier transforms fast Fourier transforms cmos logic circuits two-dimensional FFT architecture signal processing systems image reconstruction signal processing applications medical imaging computer vision FFT computation parallel unrolled radix-4 memory optimised parallel architecture data reordering discrete Fourier transforms multidimensional DFT two-dimensional fast Fourier transform application specific integrated circuit face recognition 2D FFT architecture radix-4(3) algorithm row-column decomposition UMC complementary metal oxide semiconductor power consumption Virtex 7 field programmable gate array power 358 0 mW frequency 500 0 MHz time 8 19 mus size 40 0 nm size 0 841 mm

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Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

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IET circuits DEVICES & SYSTEMS 2019年第4期13卷 534-543页

作者： Gassoumi, Ismail Touil, Lamjed Ouni, Bouraoui Univ Monastir Lab Elect & Microelect Monastir Tunisia Univ Sousse Networked Objects Control & Commun Syst Lab Sousse Tunisia Higher Inst Technol Studies Sousse Sousse Tunisia

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 mu W. The proposed circuit has 90% improvement in terms of power over complementary metal-oxide-semiconductor (cmos) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

关键词： digital filters quantum dots nanotechnology low-power electronics logic design digital signal processing chips cellular automata cmos logic circuits power dissipation analysis ultra-low power consumption multiply accumulator unit digital signal processing real-time DSP systems speech processing QCA technology complementary metal-oxide-semiconductor circuits QCA logic signal processing real-time signal image treatment quantum dot cellular automata digital filtering low power MAC unit video coding QCADesigner version 2 0 3 QCAPro tool cmos circuits power 2 183 muW

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Constant power consumption design of novel differential logic gate for immunity against differential power analysis

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IET circuits DEVICES & SYSTEMS 2019年第1期13卷 103-109页

作者： Saini, Harjap Gupta, Anu BITS Pilani Dept Elect & Elect Engn Pilani Rajasthan India

Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND-NAND, and OR-NOR which can be easily extended for n-bit inputs. The design effort is minimal as the structure is such that AND-NAND design can be used to obtain OR-NOR function by just changing the placement of inputs. These gates have 0.46x less propagation delay, and 3.7x higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz cmos 180 nm technology with a power supply of 1.8 V.

关键词： novel DPA immune design basic gates logic gates strong salience strength highly regular structure low-power electronics noninvasive side-channel attack constant power consumption design novel differential logic gate propagation delay n-bit inputs evaluation path logic design AND–NAND design integrated circuit design power consumption OR–NOR function cryptography voltage 1.8 V Cadence tool TowerJazz cmos technology power supply size 180.0 nm differential power analysis method cmos logic circuits

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An 18-Gb/s $36\times 13 -\mu \mathrm{m}^{2}\ 3.53-\mathrm{mW}\ 2^{7}-1$ PRBS Generator in 40-nm cmos

An 18-Gb/s $36\times 13 -\mu \mathrm{m}^{2}\ 3.53-\mathrm{mW...

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Junfeng Hu Zhao Zhani Qiwei Huang Jian Yang Meihuang Hu Qiyao Jiang Yuhao Guo Quan Pan School of Microelectronics Southern University of Science and Technology Shenzhen China Graduate School of Advanced Sciences of Matter Hiroshima University Higashi-Hiroshima Japan

ISBN: (数字)9781728162898

ISBN: (纸本)9781728162904

This paper presents an 18 Gb/s 2 7 -1 pseudo-random binary sequence (PRBS) generator. In the proposed PRBS, two extended truly-single-phase clock (E-TPSC) logic based DFFs are used to shorten the critical path delay and thus improve the data rate. The rest five DFFs are implemented in TSPC logic to save power consumption. Both E-TSPC and TSPC DFF occupy small area. This PRBS is designed in 40-nm cmos. The post-layout simulation results show 18-Gb/s data rate, 36×13-μm 2 core area, 3.S3-mW dc power, and 0.028-pJ/bit FOM.

关键词： binary sequences clocks cmos logic circuits flip-flops integrated circuit layout integrated circuit modelling low-power electronics power consumption random sequences cmos logic circuits integrated circuit modelling integrated circuit layout random sequences binary sequences Timing devices low-power electronics flip-flops Power consumption DC power supply

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IO Glitch Filter

IO Glitch Filter

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IEEE International Conference on Electronics and Nanotechnology (ELNANO)

作者： Harutyun Azatyan Hrayr Sahakyan Andranik Galstyan Sergo Harutyunyan Chair of Microelectronic Circuits and Systems National Polytechnic University of Armenia Yerevan Armenia

ISBN: (数字)9781728197135

ISBN: (纸本)9781728197142

In this paper one of the ways of reducing glitches that are present in the output of a simple cmos inverter is described. This is done via RC filter. In this filter instead of resistor and capacitor MOS transistors are used, which will reduce the area of the circuit with cost of increased delay. Simulations are done under 1 GHz frequency. Under this condition the glitches were reduced by 76%, going down from 250 mV to 60 mV. All researches and simulations are done using Synopsys Armenia Educational Department's SAED 32/28 nm cmos technology and HSPICE simulator.

关键词： cmos logic circuits digital filters integrated circuit design MOSFET SPICE cmos logic circuits integrated circuit design metal-oxide-semiconductor field effect transistors Digital filters SPICE glitch Filters IO Resistor Device Component cmos technology

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Investigation Of The Benefits Of Interlocked Synchronous Pipelines

Investigation Of The Benefits Of Interlocked Synchronous Pip...

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作者： Sabrina Rose Levitan Rochester Institute of Technology

学位级别：硕士

The majority of todayâs digital circuits use synchronous pipelines. As the technology nodes get smaller, these pipelines are facing problems with area, power, and timing. One of the major sources of power consumption is the global clock and stall signals. These signals have to be routed across large sections of the chip, and with regards to stalling the pipeline, often face significant timing issues. One solution, developed by Hans M. Jacobson et al., is âSynchronous Interlocked Pipelinesâ. This pipeline design combines synchronous pipelines with the handshaking of asynchronous pipelines. Asynchronous pipelines are less power intensive because they send acknowledge and request signals to neighboring stages that allow stages to turn off when not being used. Jacobson et al. use this handshaking technique to create local valid and stall signals instead of using global ones. To test the benefits of this design, an asynchronous pipeline, synchronous pipeline, and interlocked synchronous pipeline were built using a generic 45 nm library. Comparisons showed that while the asynchronous and interlocked synchronous pipelines took up 4 times more area than the synchronous pipeline, the asynchronous pipeline had the highest throughput of the three pipeline designs, followed by the interlocked synchronous pipeline. The synchronous pipeline had the worst throughput.

关键词： asynchronous circuits cmos logic circuits current-mode logic low-power electronics pipeline arithmetic Pipelines

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Low-power-delay-product radix-4 8*8 Booth multiplier in cmos

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ELECTRONICS LETTERS 2018年第6期54卷 344-+页

作者： Xue, H. Patel, R. Boppana, N. V. V. K. Ren, S. Wright State Univ Dayton OH 45435 USA

The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8 x 8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using cmos 90 nm technology with 1.2 V supply to demonstrate performance.

关键词： cmos logic circuits logic design low-power electronics multiplying circuits power consumption

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Design optimisation procedure for digital mismatch compensation in latch comparators

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IET circuits DEVICES & SYSTEMS 2018年第6期12卷 726-734页

作者： Khanfir, Leila Mouine, Jaouhar Univ Tunis El Manar Natl Engn Sch Tunis Dept Elect Engn Anal Concept & Control Syst Lab Tunis Tunisia Prince Sattam Bin Abdulaziz Univ Dept Elect Engn Al Kharj Saudi Arabia

Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7bit calibration control in a commercially available 0.18 mu m complementary metal-oxide-semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9bit calibration resolution without altering the comparator performances.

关键词： comparators (circuits) integrated circuit design calibration low-power electronics flip-flops cmos logic circuits logic design circuit optimisation compensation three-step design procedure comparator performance latch comparator simple digital sequencer calibration accuracy design optimisation procedure digital mismatch compensation digital calibration schemes high-speed operation reduced power consumption dynamic comparators calibration control calibration resolution post-layout statistical simulations complementary metal-oxide-semiconductor technology word length 7 0 bit size 0 18 mum word length 5 9 bit

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Gate diffusion input based 4-bit Vedic multiplier design

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IET circuits DEVICES & SYSTEMS 2018年第6期12卷 764-770页

作者： Garg, Ankit Joshi, Garima Panjab Univ Univ Inst Engn & Technol Chandigarh India

A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (cmos) logic is used to design a multiplier. In cmos circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay;while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using cmos and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.

关键词： field programmable gate arrays multiplying circuits cmos logic circuits logic design integrated circuit design MOSFET gate diffusion input technique Vedic multiplier design Vedic multiplication field programmable gate array implementation circuit delay complementary metal oxide semiconductor logic circuit cmos logic circuit Vedic mathematics GDI technique transistor count minimization TC minimization power dissipation supply voltage scaling bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameter word length 4 bit size 130 nm

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Design of high-speed, low-power, and area-efficient FIR filters

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IET circuits DEVICES & SYSTEMS 2018年第1期12卷 1-11页

作者： Liacha, Ahmed Oudjida, Abdelkrim K. Ferguene, Farid Bakiri, Mohammed Berrandjia, Mohamed L. CDTA Syst Architecture & Multimedia Div Algiers Algeria USTHB LRPE Lab Algiers Algeria

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2(r). The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2(r) is more specially investigated. RADIX-2(r) is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2(r) is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm cmos technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2(r) in high order filters.

关键词： adders cmos logic circuits FIR filters digital arithmetic FIR filter design multiple constant multiplication algorithm MCM algorithm RADIX-2r lowest adder cost complementary metal oxide semiconductor technology

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